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hd404654 series 4-bit single-chip microcomputer rev. 7.0 sept. 1999 description the hd404654 series is a member of the hmcs400-series of microcomputers designed to increase program productivity with large-capacity memory. each microcomputer has a high-precision dual-tone multi-frequency (dtmf) generator, three timers, serial interface, voltage comparator, and input capture circuit. the hd404654 series includes three chips: the hd404652 with 2 k-word rom; the hd404654 with 4 k- word rom; and the hd4074654 with 4 k-word prom (ztat ? version). the hd4074654 is a prom version (ztat ? microcomputer). a program can be written to the prom by a prom writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (the ztat ? version is 27256-compatible.) ztat ? : zero turn around time. ztat is a trademark of hitachi ltd. features 27 i/o pins and 5 dedicated input pins ? 10 high-current output pins: six 15-ma sinks and four 10-ma sources three timer/counters eight-bit input capture circuit two timer outputs (including two pwm outputs) one event counter input (including one double-edge function) one clock-synchronous 8-bit serial interface voltage comparator (2 channels) on-chip dtmf generator (f osc = 400 khz, 800 khz, 2 mhz, 3.58 mhz or 4 mhz) built-in oscillators ? main clock: ceramic or crystal oscillator (an external clock is also possible) six interrupt sources ? two by external sources ? four by internal sources subroutine stack up to 16 levels, including interrupts
hd404654 series 2 two low-power dissipation modes ? standby mode ? stop mode one external input for transition from stop mode to active mode instruction cycle time: 1 m s (f osc = 4 mhz at 1/4 division ratio) ? 1/4 or 1/32 division ratio can be selected by hardware two operating modes ? mcu mode ? mcu/prom mode (hd4074654) ordering information type product name model name rom (words) ram (digit) package mask rom hd404652 HD404652H 2,048 512 fp-44a hd404652s dp-42s hd404654 hd404654h 4,096 fp-44a hd404654s dp-42s ztat ? hd4074654 hd4074654h 4,096 fp-44a hd4074654s dp-42s
hd404654 series 3 pin arrangement rd /comp rd /comp tonec toner vt ref re /vc ref test osc osc reset gnd d d d d d d d d d d 0 0 1 1 0 1 2 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 dp-42s v sel r4 /so r4 /si r4 / sck r4 /evnd r3 r3 /tod r3 /toc r3 r2 r2 r2 r2 r1 r1 r1 r1 r0 / int d / int d / stopc cc 3 1 2 1 1 1 0 3 2 1 0 3 2 1 0 3 2 1 0 0 1 13 0 12 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 fp-44a re 0 /vc ref test osc 1 osc 2 reset gnd d 0 d 1 d 2 d 3 d 4 r4 /evnd r3 r3 /tod r3 /toc r3 r2 r2 r2 r2 r1 r1 0 3 2 1 0 3 2 1 0 3 2 d d d d d d / stopc d / int r0 / int r1 r1 nc 5 6 7 8 9 12 13 0 0 1 0 1 nc vt ref toner tonec rd /comp rd /comp v sel r4 /so r4 /si r4 / sck 1 1 0 0 cc 3 1 2 1 1 1 (top view)
hd404654 series 4 pin description pin number item symbol dp-42s fp-44a i/o function power supply v cc 42 38 applies power voltage gnd 11 6 connected to ground test test 7 2 i used for factory testing only: connect this pin to v cc reset reset 10 5 i resets the mcu oscillator osc 1 83i osc 2 94o port d 0 ? 9 12?1 7?6 i/o input/output pins addressed by individual bits; pins d 4 ? 9 are high-current sink pins that can each supply up to 15 ma, d 0 ?d 3 are large- current source pins that can each supply up to 10 ma d 12 , d 13 22, 23 17, 18 i input pins addressable by individual bits r0 0 ?4 3 24?0 19?1, 23?6 i/o input/output pins addressable in 4-bit units rd 0 , rd 1 , re 0 1, 2, 6 39, 40,1 i input pins addressable in 4-bit units interrupt int 0 , int 1 23, 24 18, 19 i input pins for external interrupts stop clear stopc 22 17 i input pin for transition from stop mode to active mode serial sck 1 38 34 i/o serial clock input/output pin si 1 39 35 i serial receive data input pin so 1 40 36 o serial transmit data output pin timer toc, tod 34, 35 30, 31 o timer output pins evnd 37 33 i event count input pins dtmf toner 4 42 o output pin for dtmf row signals tonec 3 41 o output pin for dtmf column signals. vt ref 5 43 reference voltage pin for dtmf signals voltage condition is v cc 3 vt ref 3 gnd. comparator comp 0 , comp 1 1, 2 39, 40 i analog input pins for voltage comparator vc ref 6 1 reference voltage pin for inputting the threshold voltage of the analog input pin. division rate sel 41 37 i input pin for selecting system clock division rate rate after reset input or after stop mode cancellation. 1/4 division rate: connect it to v cc 1/32 division rate: connect it to gnd
hd404654 series 5 block diagram reset test stopc osc osc sel v gnd system control ram (512 4 bits) w (2 bits) x (4 bits) spx (4 bits) y (4 bits) spy (4 bits) st (1 bit) ca (1 bit) a (4 bits) b (4 bits) sp (10 bits) instruction decoder pc (14 bits) rom (4,096 10 bits) (2,048 10 bits) internal address bus internal data bus external interrupt timer a timer c timer d sci1 compa- rator dtmf d port r0 port r1 port r2 port r3 port r4 port rd port re port : data bus : si g nal line alu source sink high current pins cpu d d d d d d d d d d d d 0 1 2 3 4 5 6 7 8 9 12 13 r0 0 r1 r1 r1 r1 0 1 2 3 r2 r2 r2 r2 0 1 2 3 r3 r3 r3 r3 0 1 2 3 r4 r4 r4 r4 0 1 2 3 rd rd 0 1 re 0 0 1 toc evnd tod int int 1 1 1 si so sck 0 1 vc ref comp comp vt ref toner tonec 1 2 cc internal data bus
hd404654 series 6 memory map rom memory map the rom memory map is shown in figure 1 and described below. 0 15 16 63 64 0 $000f $07ff $003f $0040 vector address zero-page subroutine (64 words) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 $0000 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f 0 1 jmpl instruction (jump to reset , stopc routine) jmpl instruction (jump to int routine) jmpl instruction (jump to timer a routine) jmpl instruction (jump to timer d, routine) jmpl instruction (jump to int routine) jmpl instruction (jump to serial 1 routine) jmpl instruction (jump to timer c, routine) not used $0010 program & pattern (hd404652) 2047 4095 $0fff program & pattern (hd404654, hd4074654) figure 1 rom memory map vector address area ($0000?000f): reserved for jmpl instructions that branch to the start addresses of the reset and interrupt routines. after mcu reset or an interrupt, program execution continues from the vector address. zero-page subroutine area ($0000?003f): reserved for subroutines. the program branches to a subroutine in this area in response to the cal instruction. pattern area ($0000?0fff): contains rom data that can be referenced with the p instruction. program area ($0000?07ff (hd404652), $0000?0fff (hd404654, hd4074654)): used for program coding. ram memory map the mcu contains a 512-digit 4-bit ram area consisting of a memory register area, a data area, and a stack area. in addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same ram memory space as a ram-mapped register area outside the above areas. the ram memory map is shown in figure 2 and described as follows.
hd404654 series 7 0 $000 $000 64 80 576 960 1023 $040 $050 4 5 6 7 0 3 12 13 14 15 8 9 11 16 17 32 35 18 19 20 63 $003 $004 $005 $006 $007 $008 $009 $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $020 $023 $032 $033 $034 $035 $03f $00e $00f w w r/w w w w w w w w w w w w r r w r/w r/w r/w $3c0 $240 ram-mapped registers memory registers (mr) not used data (432 digits) not used stack (64 digits) interrupt control bits area port mode register a serial mode register 1a serial data register 1 lower serial data register 1 upper timer mode register a miscellaneous register timer mode register c1 timer c timer mode register d2 register flag area port r0 dcr port r1 dcr port r2 dcr port r3 dcr port d to d dcr port d to d dcr port d and d dcr not used 0 3 47 89 14 15 timer read register c lower timer read register c upper timer write register c lower timer write register c upper $090 r: w: r/w: read only write only read/write $011 $012 w w r r 17 18 timer read register d lower timer read register d upper timer write register d lower timer write register d upper 144 w timer mode register d1 r/w r/w timer d timer mode register c2 21 $015 22 $016 r compare data register 23 $017 36 $024 37 $025 38 $026 39 $027 40 $028 41 $029 42 $02a 43 $02b 24 25 27 26 31 $018 $019 $01a $01b $01f $3ff compare enable register w w w 44 45 46 47 port mode register b port mode register c detection edge select register 2 serial mode register 1b system clock select register 1 not used not used port r4 dcr w w w w $02c $02d $02e $02f $031 $030 53 48 49 50 51 52 two registers are mapped on the same area. r/w r/w (pmra) (sm1a) (sr1l) (sr1u) (tma) (mis) (tmc1) (trcl/twcl) (trcu/twcu) (tmd1) (trdl/twdl) (trdu/twdu) (tmc2) (tmd2) (cdr) (cer) (tgm) (tgc) (pmrb) (pmrc) (sm1b) (ssr1) (ssr2) (esr2) (dcd0) (dcd1) (dcd2) (dcr0) (dcr1) (dcr2) (dcr3) (dcr4) not used (trcl) (trcu) (trdl) (trdu) (twcl) (twcu) (twdl) (twdu) tg mode register tg control register system clock select register 2 w w w not used not used not used not used figure 2 ram memory map
hd404654 series 8 ram-mapped register area ($000?03f): interrupt control bits area ($000?003) this area is used for interrupt control bits (figure 3). these bits can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). however, note that not all the instructions can be used for each bit. limitations on using the instructions are shown in figure 4. special function register area ($004?01a, $024?034) this area is used as mode registers and data registers for external interrupts, serial interface 1, timer/counters, and the comparator, and as data control registers for i/o ports. the structure is shown in figures 2 and 5. these registers can be classified into three types: write-only (w), read-only (r), and read/write (r/w). ram bit manipulation instructions cannot be used for these registers. register flag area ($020?023) this area is used for the wdon, and other register flags and interrupt control bits (figure 3). these bits can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). however, note that not all the instructions can be used for each bit. limitations on using the instructions are shown in figure 4. memory register (mr) area ($040?04f): consisting of 16 addresses, this area (mr0?r15) can be accessed by register-register instructions (lamr and xmra). the structure is shown in figure 6. data area ($090?23f): 432 digits from $090 to $23f. stack area ($3c0?3ff): used for saving the contents of the program counter (pc), status flag (st), and carry flag (ca) at subroutine call (cal or call instruction) and for interrupts. this area can be used as a 16-level nesting subroutine stack in which one level requires four digits. the data to be saved and the save conditions are shown in figure 6. the program counter is restored by either the rtn or rtni instruction, but the status and carry flags can only be restored by the rtni instruction. any unused space in this area is used for data storage.
hd404654 series 9 0 1 2 3 bit 3 bit 2 bit 1 bit 0 imta (im of timer a) ifta (if of timer a) im1 (im of int 1 ) if1 (if of int 1 ) imtc (im of timer c) iftc (if of timer c) ims1 (im of serial interface 1) ifs1 (if of serial interface 1) imtd (im of timer d) iftd (if of timer d) $000 $001 $002 $003 interrupt control bits area im0 (im of int 0 ) if0 (if of int 0 ) rsp (reset sp bit) ie (interrupt enable flag) 32 33 icsf (input capture status flag) $020 $021 register flag area wdon (watchdog on flag) icef (input capture error flag) rame (ram enable flag) not used if: im: ie: sp: interrupt request flag interrupt mask interrupt enable flag stack pointer bit 3 bit 2 bit 1 bit 0 not used not used not used not used not used figure 3 configuration of interrupt control bits and register flag areas ie im if icsf icef rame rsp wdon not used sem/semd rem/remd tm/tmd allowed allowed allowed not executed allowed allowed not executed allowed inhibited allowed not executed inhibited not executed not executed inhibited note: wdon is reset by mcu reset or by stopc enable for stop mode cancellation. if the tm or tdm instruction is executed for the inhibited bits or non-existing bits, the value in st becomes invalid. figure 4 usage limitations of ram bit manipulation instructions
hd404654 series 10 $000 $003 pmra $004 sm1a $005 sr1l $006 sr1u $007 tma $008 mis $00c tmc1 $00d trcl/twcl $00e trcu/twcu $00f tmd1 $010 trdl/twdl $011 trdu/twdu $012 $013 tmc2 $014 tmd2 $015 $016 cdr $017 cer $018 tgm $019 tgc $01a $020 $023 pmrb $024 pmrc $025 $026 esr2 $027 sm1b $028 ssr1 $029 ssr2 $02a dcd0 $02c dcd1 $02d dcd2 $02e dcr0 $030 dcr1 $031 dcr2 $032 dcr3 $033 dcr4 $034 $03f bit 3 bit 2 bit 1 interrupt control bits area : not used r4 2 /si 1 r4 3 /so 1 serial transmit clock speed selection 1 serial data register 1 (lower digit) serial data register 1 (upper digit) clock source selection (timer a) 2 so 1 pmos control interrupt frame period selection 1 clock source selection (timer c) timer c register (lower digit) timer c register (upper digit) 1 clock source selection (timer d) timer d register (lower digit) timer d register (upper digit) timer-c output mode selection timer-d output mode selection 3 result of each analog input comparison register flag area r4 0 /evnd evnd detection edge selection 8 9 port d 3 dcr port d 7 dcr port d 2 dcr port d 6 dcr port d 1 dcr port d 5 dcr port d 9 dcr port d 0 dcr port d 4 dcr port d 8 dcr port r1 3 dcr port r2 3 dcr port r3 3 dcr port r4 3 dcr port r1 2 dcr port r2 2 dcr port r3 2 dcr port r4 2 dcr port r1 1 dcr port r2 1 dcr port r3 1 dcr port r4 1 dcr port r0 0 dcr port r1 0 dcr port r2 0 dcr port r3 0 dcr port r4 0 dcr d 12 / stopc d 13 / int 0 r0 0 / int 1 r4 1 / sck 1 bit 0 system clock selection 4 5 6 7 tonec output frequency toner output frequency dtmf enable 10 1. auto-reload on/off 2. pull-up mos control 3. input capture selection 4. comparator switch 5. port/comparator selection 6. tonec output control 7. toner output control 8. so 1 output level control in idle states 9. serial clock source selection 1 10. system clock selection notes: * * * * * * ** * * * figure 5 special function register area
hd404654 series 11 memory registers 64 65 66 67 68 69 70 71 73 74 75 76 77 78 79 72 $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04a $04b $04c $04d $04e $04f 960 $3c0 1023 $3ff mr(0) mr(1) mr(2) mr(3) mr(4) mr(5) mr(6) mr(7) mr(8) mr(9) level 16 level 15 level 14 level 13 level 12 level 11 level 10 level 9 level 8 level 7 level 6 level 5 level 4 level 3 level 2 level 1 mr(10) mr(11) mr(12) mr(13) mr(14) mr(15) pc pc pc pc pc pc pc pc pc pc pc pc st pc ca pc 10 3 13 9 6 2 12 8 5 1 11 7 4 0 bit 3 bit 2 bit 1 bit 0 $3fc $3fd $3fe $3ff 1020 1021 1022 1023 pc ?c : st: status flag ca: carry flag program counter 13 stack area 0 figure 6 configuration of memory registers and stack area, and stack position
hd404654 series 12 functional description registers and flags the mcu has nine registers and two flags for cpu operations. they are shown in figure 7 and described below. 30 30 30 30 30 30 0 0 0 13 95 1 (b) (a) (w) (x) (y) (spx) (spy) (ca) (st) (pc) (sp) 1111 accumulator b register w register x register y register spx register spy register carry status program counter initial value: 0, no r/w stack pointer initial value: $3ff, no r/w 0 0 initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: 1, no r/w figure 7 registers and flags accumulator (a), b register (b): four-bit registers used to hold the results from the arithmetic logic unit (alu) and transfer data between memory, i/o, and other registers. w register (w), x register (x), y register (y): two-bit (w) and four-bit (x and y) registers used for indirect ram addressing. the y register is also used for d-port addressing.
hd404654 series 13 spx register (spx), spy register (spy): four-bit registers used to supplement the x and y registers. carry flag (ca): one-bit flag that stores any alu overflow generated by an arithmetic operation. ca is affected by the sec, rec, rotl, and rotr instructions. a carry is pushed onto the stack during an interrupt and popped from the stack by the rtni instruction?ut not by the rtn instruction. status flag (st): one-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the alu, or result of a bit test. st is used as a branch condition of the br, brl, cal, and call instructions. the contents of st remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the br, brl, cal, or call instruction is read, regardless of whether the instruction is executed or skipped. the contents of st are pushed onto the stack during an interrupt and popped from the stack by the rtni instruction?ut not by the rtn instruction. program counter (pc): 14-bit binary counter that points to the rom address of the instruction being executed. stack pointer (sp): ten-bit pointer that contains the address of the stack area to be used next. the sp is initialized to $3ff by mcu reset. it is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. the top four bits of the sp are fixed at 1111, so a stack can be used up to 16 levels. the sp can be initialized to $3ff in another way: by resetting the rsp bit with the rem or remd instruction. reset the mcu is reset by inputting a high-level voltage to the reset pin. at power-on or when stop mode is cancelled, reset must be high for at least one t rc to enable the oscillator to stabilize. during operation, reset must be high for at least two instruction cycles. initial values after mcu reset are listed in table 1. interrupts the mcu has 6 interrupt sources: two external signals ( int 0 , int 1 ), three timer/counters (timers a, c, and d), and one serial interface (serial 1). an interrupt request flag (if), interrupt mask (im), and vector address are provided for each interrupt source, and an interrupt enable flag (ie) controls the entire interrupt process. interrupt control bits and interrupt processing: locations $000 to $003 and $020 to $021 in ram are reserved for the interrupt control bits which can be accessed by ram bit manipulation instructions. the interrupt request flag (if) cannot be set by software. mcu reset initializes the interrupt enable flag (ie) and the if to 0 and the interrupt mask (im) to 1.
hd404654 series 14 a block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in table 3. an interrupt request occurs when the if is set to 1 and the im is set to 0. if the ie is 1 at that point, the interrupt is processed. a priority programmable logic array (pla) generates the vector address assigned to that interrupt source. the interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in figure 10. after an interrupt is acknowledged, the previous instruction is completed in the first cycle. the ie is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. program the jmpl instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the if by a software instruction within the interrupt program.
hd404654 series 15 table 1 initial values after mcu reset item abbr. initial value contents program counter (pc) $0000 indicates program execution point from start address of rom area status flag (st) 1 enables conditional branching stack pointer (sp) $3ff stack level 0 interrupt flags/mask interrupt enable flag (ie) 0 inhibits all interrupts interrupt request flag (if) 0 indicates there is no interrupt request interrupt mask (im) 1 prevents (masks) interrupt requests i/o port data register (pdr) all bits 1 enables output at level 1 data control register (dcd0 dcd2) all bits 0 turns output buffer off (to high impedance) (dcr0 dcr4) all bits 0 port mode register a (pmra) - - 00 refer to description of port mode register a port mode register b (pmrb) - - - 0 refer to description of port mode register b port mode register c bits 3, 1, 0 (pmrc3, pmrc1, pmrc0) 000 - refer to description of port mode register c detection edge select register 2 (esr2) 00 - - disables edge detection timer/counters, serial interface timer mode register a (tma) - 000 refer to description of timer mode register a timer mode register c1 (tmc1) 0000 refer to description of timer mode register c1 timer mode register c2 (tmc2) - 000 refer to description of timer mode register c2 timer mode register d1 (tmd1) 0000 refer to description of timer mode register d1 timer mode register d2 (tmd2) 0000 refer to description of timer mode register d2 serial mode register 1a (sm1a) 0000 refer to description of serial mode register 1a serial mode register 1b (sm1b) - - x0 refer to description of serial mode register 1b prescaler s (pss) $000 timer counter a (tca) $00
hd404654 series 16 item abbr. initial value contents timer/counters, serial interface timer counter c (tcc) $00 timer counter d (tcd) $00 timer write register c (twcu, twcl) $x0 timer write register d (twdu, twdl) $x0 octal counter 000 comparator compare enable register (cer) 0 - 00 refer to description of voltage comparator bit register watchdog timer on flag (wdon) 0 refer to description of timer c input capture status flag (icsf) 0 refer to description of timer d input capture error flag (icef) 0 refer to description of timer d others miscellaneous register (mis) 00 - - refer to description of operating modes, and oscillator circuit system clock select register 1 bits 1, 0 (ssr11, ssr10) 00 refer to description of operating modes, and oscillator circuit system clock select register 2 (ssr2) - 0 - - notes: 1. the statuses of other registers and flags after mcu reset are shown in the following table. 2. x indicates invalid value. ?indicates that the bit does not exist.
hd404654 series 17 item abbr. status after cancellation of stop mode by stopc input status after cancellation of stop mode by mcu reset status after all other types of reset carry flag (ca) pre-stop-mode values are not guaranteed; values must be initialized by program pre-mcu-reset values are not guaranteed; values must be initialized by program accumulator (a) b register (b) w register (w) x/spx register (x/spx) y/spy register (y/spy) serial data register (srl, sru) ram pre-stop-mode values are retained ram enable flag (rame) 1 0 0 port mode register 1 bit 2 (pmrc12) pre-stop-mode values are retained 00 system clock select register 1 bit 3 (ssr13) table 2 vector addresses and interrupt priorities reset/interrupt priority vector address reset , stopc * $0000 int 0 1 $0002 int 1 2 $0004 timer a 3 $0006 not used 4 $0008 timer c 5 $000a timer d 6 $000c serial 1 7 $000e note: * the stopc interrupt request is valid only in stop mode.
hd404654 series 18 ie ifo imo if1 im1 ifta imta iftc imtc iftd imtd $ 000,0 $ 000,2 $ 000,3 $ 001,0 $ 001,1 $ 001,2 $ 001,3 $ 002,2 $ 002,3 $ 003,0 $ 003,1 sequence control ?push pc/ca/st ?reset ie ?jump to vector address priority control logic vector address note: $m,n is ram address $m, bit number n. $ 003,2 $ 003,3 int 0 interrupt int 1 interrupt timer a interrupt timer c interrupt timer d interrupt serial interrupt ifs1 ims1 not used figure 8 interrupt control circuit
hd404654 series 19 table 3 interrupt processing and activation conditions interrupt source interrupt control bit int 0 int 1 timer a timer c timer d serial 1 ie 111111 if0 im0 100000 if1 im1 * 10000 ifta imta ** 1000 iftc ? imtc *** 100 iftd ? imtd **** 10 ifs1 ims1 ***** 1 note: * can be either 0 or 1. their values have no effect on operation. instruction cycles 123456 instruction execution ie reset interrupt acceptance execution of jmpl instruction at vector address execution of instruction at start address of interrupt routine vector address generation note: the stack is accessed and the ie reset after the instruction is executed, even if it is a two-cycle instruction. * stacking * figure 9 interrupt processing sequence
hd404654 series 20 power on reset = 0? reset mcu interrupt request? execute instruction pc (pc) + 1 ? pc $0002 ? pc $0004 ? pc $0006 ? pc $000a ? ie = 1? accept interrupt ie 0 stack (pc) stack (ca) stack (st) ? int 0 interrupt? int 1 interrupt? timer-a interrupt? no yes no yes no yes yes yes yes yes no no no ? ? ? (serial 1 interrupt) pc $000c ? timer-d interrupt? yes no no timer-c interrupt? pc $000e ? figure 10 interrupt processing flowchart
hd404654 series 21 interrupt enable flag (ie: $000, bit 0): controls the entire interrupt process. it is reset by the interrupt processing and set by the rtni instruction, as listed in table 4. table 4 interrupt enable flag (ie: $000, bit 0) ie interrupt enabled/disabled 0 disabled 1 enabled external interrupts ( int 0 , int 1 ): two external interrupt signals. external interrupt request flags (if0, if1: $000, $001): if0 and if1 are set at the falling edge of signals input to int 0 and int 1 as listed in table 5. table 5 external interrupt request flags (if0, if1: $000, $001) if0, if1 interrupt request 0no 1 yes external interrupt masks (im0, im1: $000, $001): prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. table 6 external interrupt masks (im0, im1: $000, $001) im0, im1 interrupt request 0 enabled 1 disabled (masked) timer a interrupt request flag (ifta: $001, bit 2): set by overflow output from timer a, as listed in table 7. table 7 timer a interrupt request flag (ifta: $001, bit 2) ifta interrupt request 0no 1 yes timer a interrupt mask (imta: $001, bit 3): prevents (masks) an interrupt request caused by the timer a interrupt request flag, as listed in table 8.
hd404654 series 22 table 8 timer a interrupt mask (imta: $001, bit 3) imta interrupt request 0 enabled 1 disabled (masked) timer c interrupt request flag (iftc: $002, bit 2): set by overflow output from timer c, as listed in table 9. table 9 timer c interrupt request flag (iftc: $002, bit 2) iftc interrupt request 0no 1 yes timer c interrupt mask (imtc: $002, bit 3): prevents (masks) an interrupt request caused by the timer c interrupt request flag, as listed in table 10. table 10 timer c interrupt mask (imtc: $002, bit 3) imtc interrupt request 0 enabled 1 disabled (masked) timer d interrupt request flag (iftd: $003, bit 0): set by overflow output from timer d, or by the rising or falling edge of signals input to evnd when the input capture function is used, as listed in table 11. table 11 timer d interrupt request flag (iftd: $003, bit 0) iftd interrupt request 0no 1 yes timer d interrupt mask (imtd: $003, bit 1): prevents (masks) an interrupt request caused by the timer d interrupt request flag, as listed in table 12.
hd404654 series 23 table 12 timer d interrupt mask (imtd: $003, bit 1) imtd interrupt request 0 enabled 1 disabled (masked) serial interrupt request flags (ifs1: $003, bit 2): set when data transfer is completed or when data transfer is suspended, as listed in table 13. table 13 serial interrupt request flag (ifs1: $003, bit 2) ifs1 interrupt request 0no 1 yes serial interrupt masks (ims1: $003, bit 3): prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 14. table 14 serial interrupt mask (ims1: $003, bit 3) ims1 interrupt request 0 enabled 1 disabled (masked)
hd404654 series 24 operating modes the mcu has three operating modes as shown in table 15. the operations in each mode are listed in tables 16 and 17. transitions between operating modes are shown in figure 11. table 15 operating modes and clock status mode name active standby stop activation method reset cancellation, interrupt request, stopc cancellation in stop mode sby instruction stop instruction status system oscillator op op stopped cancellation method reset input, stop/sby instruction reset input, interrupt request reset input, stopc input in stop mode note: op implies in operation table 16 operations in low-power dissipation modes function stop mode standby mode cpu reset retained ram retained retained timer a reset op timer c reset op timer d reset op serial 1 reset op dtmf reset op comparator reset stopped i/o reset * retained notes: op implies in operation * output pins are at high impedance.
hd404654 series 25 table 17 i/o status in low-power dissipation modes output input standby mode stop mode active mode d 0 ? 9 retained high impedance input enabled d 12 ? 13 , rd 0 , rd 1 , re 0 input enabled r0?4 retained or output of peripheral functions high impedance input enabled reset by reset input or by watchdog timer f osc : cpu : ? per : oscillate stop f cyc f osc : cpu : per : oscillate f cyc f cyc f osc : cpu : per : standby mode (tma3 = 0) sby interrupt f osc : f cyc : main oscillation frequency f /4 or or f /32 (hardware selectable) osc system clock clock for other peripheral functions active mode cpu : ? per reset1 reset2 rame = 0 rame = 1 stopc stop osc stop stop stop stop mode figure 11 mcu status transitions active mode: all mcu functions operate according to the clock generated by the system oscillators osc 1 and osc 2 . standby mode: in standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. therefore, the cpu operation stops, but all ram and register contents are retained, and the d or r port status, when set to output, is maintained. peripheral functions such as interrupts, timers, and serial interface continue to operate. the power dissipation in this mode is lower than in active mode because the cpu stops. the mcu enters standby mode when the sby instruction is executed in active mode. standby mode is terminated by a reset input or an interrupt request. if it is terminated by reset input, the mcu is reset as well. after an interrupt request, the mcu enters active mode and executes the next instruction after the sby instruction. if the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. a flowchart of operation in standby mode is shown in figure 12.
hd404654 series 26 standby oscillator: active peripheral clocks: active all other clocks: stop no yes no yes no yes no yes no yes yes restart processor clocks reset mcu execute next instruction accept interrupt restart processor clocks no yes if = 1, im = 0, and ie = 1? reset = 0? if0 ? im0 = 1? if1 ? im1 = 1? ifta ? imta = 1? iftc ? imtc = 1? iftd ? imtd = 1? no yes ifs1 ? ims1 = 1? no stop oscillator: stop peripheral clocks: stop all other clocks: stop reset = 0? stopc = 0? rame = 1 rame = 0 yes yes no no execute next instruction figure 12 mcu operation flowchart stop mode: in stop mode, all mcu operations stop and ram data is retained. therefore, the power dissipation in this mode is the least of all modes. the osc 1 and osc 2 oscillator stops. the mcu enters stop mode if the stop instruction is executed in active mode. stop mode is terminated by a reset input or a stopc input as shown in figure 13. reset or stopc must be applied for at least one t rc to stabilize oscillation (refer to the ac characteristics section). when the mcu restarts after stop mode is cancelled, all ram contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, b register, w register, x/spx register, y/spy register, carry flag, and serial data register cannot be guaranteed.
hd404654 series 27 stop mode cancellation by stopc : the mcu enters active mode from stop mode by inputting stopc as well as by reset . in either case, the mcu starts instruction execution from the starting address (address 0) of the program. however, the value of the ram enable flag (rame: $021, bit 3) differs between cancellation by stopc and by reset . when stop mode is cancelled by reset , rame = 0; when cancelled by stopc , rame = 1. reset can cancel all modes, but stopc is valid only in stop mode; stopc input is ignored in other modes. therefore, when the program requires to confirm that stop mode has been cancelled by stopc (for example, when the ram contents before entering stop mode are used after transition to active mode), execute the test instruction on the ram enable flag (rame) at the beginning of the program.

stop mode oscillator internal clock stop instruction execution t res 3 t rc (stabilization period) t res stopc or reset figure 13 timing of stop mode cancellation
hd404654 series 28 mcu operation sequence: the mcu operates in the sequences shown in figures 14 to 16. it is reset by an asynchronous reset input, regardless of its status. the low-power mode operation sequence is shown in figure 16. with the ie flag cleared and an interrupt flag set together with its interrupt mask cleared, if a stop/sby instruction is executed, the instruction is cancelled (regarded as an nop) and the following instruction is executed. before executing a stop/sby instruction, make sure all interrupt flags are cleared or all interrupts are masked. power on reset = 0? rame = 0 reset mcu mcu operation cycle no yes figure 14 mcu operating sequence (power on)
hd404654 series 29 mcu operation cycle if = 1? instruction execution sby/stop instruction? pc next location pc vector address low-power mode operation cycle ie 0 stack (pc), (ca), (st) im = 0 and ie = 1? ? ? ? yes no no yes yes no if: im: ie: pc: ca: st: ? interrupt request flag interrupt mask interrupt enable flag program counter carry flag status flag figure 15 mcu operating sequence (mcu operation cycle)
hd404654 series 30 low-power mode operation cycle if = 1 and im = 0? hardware nop execution ? pc next iocation mcu operation cycle standby mode if = 1 and im = 0? hardware nop execution pc next iocation ? instruction execution stop mode no yes no yes for if and im operation, refer to figure 12. stopc = 0? rame = 1 reset mcu no yes figure 16 mcu operating sequence (low-power mode operation)
hd404654 series 31 internal oscillator circuit a block diagram of the clock generation circuit is shown in figure 17. as shown in table 18, a ceramic oscillator or crystal oscillator can be connected to osc 1 and osc 2 . the system oscillator can also be operated by an external clock. bit 1 (ssr11) of system clock select register 1 (ssr1: $029) and bit 2 (ssr22) of system clock select register 2 (ssr2: $02a) must be selected according to the frequency of the oscillator connected to osc 1 and osc 2 (figure 18). note: if the ssr10, ssr11 and ssr22 setting does not match the oscillator frequency, the dtmf generator will malfunction. after reset input or after stop mode has been cancelled, the division ratio of the system clock can be selected as 1/4 or 1/32 by setting the sel pin level. 1/4 division ratio: connect sel to v cc . 1/32 division ratio: connect sel to gnd. osc 2 osc 1 system oscillator 1/4 or 1/32 division circuit * timing generator circuit cpu with rom, ram, registers, flags, and i/o peripheral function interrupt f cyc t cyc f osc f cpu f per note: * 1/4 or 1/32 division ratio can be selected by pin sel. figure 17 clock generation circuit
hd404654 series 32 bit initial value read/write bit name 3 not used 2 not used 0 0 w ssr10 1 0 w ssr11 system clock select register 1 (ssr1: $029) system clock selection 400 khz 800 khz 2 mhz 4 mhz 3.58 mhz ssr10 0 1 0 1 ssr11 0 0 1 1 ssr22 0 0 0 0 1 : don? care figure 18 system clock select register 1 bit initial value read/write bit name 3 not used 2 0 w ssr22 0 not used 1 not used system clock select register 2 (ssr2: $02a) ssr22 0 1 system clock selection selected from 400 khz, 800 khz, 2 mhz, 4 mhz note: * 3.58 mhz * refer to system clock select register 1 (ssr1) of figure 18. figure 19 system clock select register 2
hd404654 series 33 osc 2 gnd reset osc 1 re 0 test gnd figure 20 typical layout of crystal and ceramic oscillators
hd404654 series 34 table 18 oscillator circuit examples circuit configuration circuit constants external clock operation external oscillator osc open 1 osc 2 ceramic oscillator (osc 1 , osc 2 ) osc 2 c 1 2 c osc 1 r f ceramic oscillator gnd ceramic oscillator: csb400p22 (murata), csb400p (murata) r f = 1 m w 20% c 1 = c 2 = 220 pf 5% ceramic oscillator: csb800j122 (murata), csb800j (murata) r f = 1 m w 20% c 1 = c 2 = 220 pf 5% ceramic oscillator: csa2.00mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% ceramic oscillator: csa4.00mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% ceramic oscillator: csa3.58mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% notes: 1. since the circuit constants change depending on the ceramic oscillator and stray capacitance of the board, the user should consult with the ceramic oscillator manufacturer to determine the circuit parameters. 2. wiring among osc 1 , osc 2 , and elements should be as short as possible, and must not cross other wiring (see figure 20).
hd404654 series 35 input/output the mcu has 27 input/output pins (d 0 ? 9 , r0 0 ?4 3 ) and 5 input pins (d 12 , d 13, rd 0 , rd 1 , re 0 ). the features are described below. a maximum current of 15 ma is allowed for each of the pins d 4 to d 9 with a total maximum current of less than 105 ma. in addition, d 0 ? 3 can each act as a 10-ma maximum current source. some input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. for these pins, the peripheral function setting is done prior to the d or r port setting. therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. peripheral function output pins are cmos output pins. only the r4 3 /so 1 pin can be set to nmos open- drain output by software. in stop mode, the mcu is reset, and therefore peripheral function selection is cancelled. input/output pins are in high-impedance state. pins d 0 ? 3 have built-in pull-down moss, and other input/output pins have built-in pull-up moss, which can be individually turned on or off by software. the i/o buffer configuration is shown in figure 21 and 22, programmable i/o circuits are listed in table 19, and i/o pin circuit types are shown in table 20. table 19 programmable i/o circuits mis3 (bit 3 of mis) 0 1 dcd, dcr 0 1 0 1 pdr 01010 101 cmos buffer pmos ?n on nmos on on pull-up mos on?n pull-down mos onon note: ?indicates off status.
hd404654 series 36 d 4 ? 9 , r port mis3 input control signal v cc pull-up mos dcd, dcr pdr input data v cc hlt pull-up control signal buffer control signal output data figure 21 i/o buffer configuration (with pull-up mos) d 0 ? 3 port v cc dcd pdr pull-down control signal buffer control signal output data mis3 hlt input control signal input data figure 22 i/o buffer configuration (with pull-down mos)
hd404654 series 37 table 20-1 circuit configurations of i/o pins i/o pin type circuit pins input/output pins v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 dcd, dcr pdr input control signal d 4 ? 9 , r0 0 , r1 0 ?1 3 , r2 0 ?2 3 r3 0 ?3 3, r4 0 ?4 2 v cc dcd pdr pull-down control signal buffer control signal output data mis3 hlt input control signal input data d 0 ? 3 v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 dcr pdr input control signal mis2 r4 3 input pins input data input control signal d 12 , d 13 rd 0 , rd 1 , re 0
hd404654 series 38 i/o pin type circuit pins peripheral function pins input/ output pins v cc v cc pull-up control signal output data input data hlt mis3 sck 1 sck 1 sck 1 peripheral function pins output pins v cc v cc pull-up control signal pmos control signal output data hlt mis3 so 1 mis2 so 1 v cc v cc pull-up control signal output data hlt mis3 toc, tod toc, tod input pins input data si 1 , int 1 , evnd hlt mis3 pdr v cc si 1 , int 1 , evnd input data int 0 , stopc int 0 , stopc note: the mcu is reset in stop mode, and peripheral function selection is cancelled. the hlt signal becomes low, and input/output pins enter high-impedance state. d port (d 0 ? 13 ): consist of 10 input/output pins and 2 input pins addressed by one bit. d 0 ? 3 are high- current sources, d 4 ? 9 are large-current sinks, and d 12 and d 13 are input-only pins. pins d 0 ? 9 are set by the sed and sedd instructions, and reset by the red and redd instructions. output data is stored in the port data register (pdr) for each pin. all pins d 0 ? 13 are tested by the td and tdd instructions. the on/off statuses of the output buffers are controlled by d-port data control registers (dcd0?cd2: $02c?02e) that are mapped to memory addresses (figure 23).
hd404654 series 39 pins d 12 and d 13 are multiplexed with peripheral function pins stopc and i nt 0 , respectively. the peripheral function modes of these pins are selected by bits 2 and 3 (pmrc2, pmrc3) of port mode register c (pmrc: $025) (figure 24). r ports (r0 0 , r1 0 ?4 3 , rd 0 , rd 1 , re 0 ): 17 input/output pins and 3 input pins addressed in 4-bit units. data is input to these ports by the lar and lbr instructions, and output from them by the lra and lrb instructions. output data is stored in the port data register (pdr) for each pin. the on/off statuses of the output buffers of the r ports are controlled by r-port data control registers (dcr0?cr4: $030?034) that are mapped to memory addresses (figure 23). pin r0 0 is multiplexed with peripheral pin int 1 . the peripheral function mode of this pins is selected by bit 0 (pmrb0) of port mode register b (pmrb: $024) (figure 25). pins r3 1 ?3 2 are multiplexed with peripheral pins toc and tod respectively. the peripheral function modes of these pins are selected by bits 0? (tmc20?mc22) of timer mode register c2 (tmc2: $014), and bits 0? (tmd20?md23) of timer mode register d2 (tmd2: $015) (figures 26, and 27). pin r4 0 is multiplexed with peripheral pin evnd. the peripheral function mode of this pins is selected by bit 1 (pmrc1) of port mode register c (pmrc: $025) (figure 24). pins r4 1 ?4 3 are multiplexed with peripheral pins sck 1 , si 1 , and so 1 , respectively. the peripheral function modes of these pins are selected by bit 3 (sm1a3) of serial mode register 1a (sm1a: $005), and bits 0 and 1 (pmra0, pmra1) of port mode register a (pmra: $004), as shown in figures 28 and 29. ports rd 0 and rd 1 are multiplexed with peripheral function pins comp 0 and comp 1 , respectively. the function modes of these pins are selected by bit 3 (cer3) of the compare enable register (cer: $018), as shown in figure 30. port re 0 is multiplexed with peripheral function pin vc ref . while functioning as vc ref , do not use this pin as an r port at the same time, otherwise, the mcu may malfunction. pull-up or pull-down mos transistor control: a program-controlled pull-up or pull-down mos transistor is provided for each input/output pin other than input-only pins d 12 and d 13 . the on/off status of all these transistors is controlled by bit 3 (mis3) of the miscellaneous register (mis: $00c), and the on/off status of an individual transistor can also be controlled by the port data register (pdr) of the corresponding pin?nabling on/off control of that pin alone (table 19 and figure 31). the on/off status of each transistor and the peripheral function mode of each pin can be set independently. how to deal with unused i/o pins: i/o pins that are not needed by the user system (floating) must be connected to v cc to prevent lsi malfunctions due to noise. these pins must either be pulled up to v cc by their pull-up mos transistors or by resistors of about 100 k w or pulled down to gnd by their pull-down mos transistors.
hd404654 series 40 dcd0, dcd1 bit initial value read/write bit name 3 0 w dcd03, dcd13 2 0 w dcd02, dcd12 0 0 w dcd00, dcd10 1 0 w dcd01, dcd11 data control register (dcd0 to 2: $02c to $02e) (dcr0 to 4: $030 to $034) dcd2 bit initial value read/write bit name 3 not used 2 not used 0 0 w dcd20 1 0 w dcd21 dcr0 bit initial value read/write bit name 3 not used 2 not used 0 0 w dcr00 1 not used dcr1 to dcr4 bit initial value read/write bit name 3 0 w dcr13 dcr43 2 0 w dcr12 dcr42 0 0 w dcr10 dcr40 1 0 w dcr11 dcr41 correspondence between ports and dcd/dcr bits 0 1 dcd0 dcd1 dcd2 dcr0 dcr1 dcr2 dcr3 dcr4 off (high-impedance) on all bits cmos buffer on/off selection register name d 3 d 7 r1 3 r2 3 r3 3 r4 3 bit 3 d 2 d 6 r1 2 r2 2 r3 2 r4 2 bit 2 d 1 d 5 d 9 r1 1 r2 1 r3 1 r4 1 bit 1 d 0 d 4 d 8 r0 0 r1 0 r2 0 r3 0 r4 0 bit 0 figure 23 data control registers (dcd, dcr)
hd404654 series 41 bit initial value read/write bit name 3 0 w pmrc3 2 0 w pmrc2 * 0 not used 1 0 w pmrc1 port mode register c (pmrc: $025) pmrc1 0 1 r4 0 /evnd mode selection r4 0 evnd pmrc2 0 1 d 12 stopc pmrc3 0 1 d 13 d 13 / int 0 mode selection int 0 d 12 / stopc mode selection note: * pmrc2 is reset to 0 only by reset input. when stopc is input in stop mode, pmrc2 is not reset but retains its value. figure 24 port mode register c (pmrc ) bit initial value read/write bit name 3 not used 2 not used 0 0 w pmrb0 1 not used port mode register b (pmrb: $024) pmrb0 0 1 r0 0 / int 1 mode selection r0 0 int 1 figure 25 port mode register b (pmrb)
hd404654 series 42 bit initial value read/write bit name 3 not used 2 0 r/w tmc22 0 0 r/w tmc20 1 0 r/w tmc21 timer mode register c2 (tmc2: $014) tmc22 tmc20 0 1 0 1 0 1 0 1 tmc21 0 1 0 1 0 1 r3 1 /toc mode selection r3 1 toc toc toc toc r3 1 port toggle output 0 output 1 output inhibited pwm output figure 26 timer mode register c2 (tmc2)
hd404654 series 43 bit initial value read/write bit name 3 0 r/w tmd23 2 0 r/w tmd22 0 0 r/w tmd20 1 0 r/w tmd21 timer mode register d2 (tmd2: $015) tmd22 tmd20 0 1 0 1 0 1 0 1 tmd21 0 1 0 1 0 1 r3 2 /tod mode selection r3 2 tod tod tod tod r3 2 r3 2 port toggle output 0 output 1 output inhibited pwm output input capture (r3 2 port) tmd23 0 1 don? care don? care don? care figure 27 timer mode register d2 (tmd2)
hd404654 series 44 bit initial value read/write bit name 3 0 w sm1a3 2 0 w sm1a2 0 0 w sm1a0 1 0 w sm1a1 serial mode register 1a (sm1a: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 output output output output output output output input prescaler prescaler prescaler prescaler prescaler prescaler system clock external clock ? 2048 ? 512 ? 128 ? 32 ? 8 ? 2 prescaler division ratio sm1a2 sm1a0 sm1a1 clock source sm1a3 0 1 r4 1 / sck 1 mode selection sck 1 r4 1 sck 1 figure 28 serial mode register 1a (sm1a) pmra0 0 1 r4 3 /so 1 mode selection r4 3 so 1 bit initial value read/write bit name 2 not used 0 0 w pmra0 1 0 w pmra1 port mode register a (pmra: $004) pmra1 0 1 r4 2 /si 1 mode selection r4 2 si 1 3 not used figure 29 port mode register a (pmra)
hd404654 series 45 bit initial value read/write bit name 3 0 w cer3 2 not used 0 0 w cer0 1 0 w cer1 compare enable register (cer: $018) cer1 0 0 1 1 analog input pin selection comp 0 comp 1 not used not used cer3 digital input mode: rd /comp 0 and rd /comp 1 operate as an r port. digital/analog selection analog input mode: rd /comp 0 and rd /comp 1 operate as analog input. 0 1 cer0 0 1 0 1 01 01 figure 30 compare enable register bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 mis2 cmos buffer on/off selection for pin r4 3 /so 1 miscellaneous register (mis: $00c) 0 1 on off mis3 0 1 pull-up mos on/off selection off on 0 not used 1 not used figure 31 miscellaneous register (mis)
hd404654 series 46 prescalers the mcu has the following prescaler s. the prescaler operating conditions are listed in table 21, and the prescaler output supply is shown in figure 32. the timer a? input clocks except external events and the serial transmit clock except the external clock are selected from the prescaler outputs, depending on corresponding mode registers. prescaler operation prescaler s: 11-bit counter that inputs a system clock signal. after being reset to $000 by mcu reset, prescaler s divides the system clock. prescaler s keeps counting, except at mcu reset. table 21 prescaler operating conditions prescaler input clock reset condition stop conditions prescaler s system clock mcu reset mcu reset, stop mode system clock prescaler s timer a timer c timer d serial 1 figure 32 prescaler output supply
hd404654 series 47 timers the mcu has three timer/counters (a, c, and d). timer a: free-running timer timer c: multifunction timer timer d: multifunction timer timer a is an 8-bit free-running timer. timers c and d are 8-bit multifunction timers, whose functions are listed in table 22. the operating modes are selected by software. table 22 timer functions functions timer a timer c timer d clock source prescaler s available available available external event available timer functions free-running available available available event counter available reload available available watchdog available input capture available timer outputs toggle available available 0 output available available 1 output available available pwm available available note: ?means not available.
hd404654 series 48 timer a timer a functions: timer a has the following functions. free-running timer the block diagram of timer a is shown in figure 33. system clock selector prescaler s (pss) internal data bus timer a interrupt request flag (ifta) clock overflow timer counter a (tca) timer mode register a (tma) 3 per 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? figure 33 block diagram of timer a timer a operations: free-running timer operation: the input clock for timer a is selected by timer mode register a (tma: $008). timer a is reset to $00 by mcu reset and incremented at each input clock. if an input clock is applied to timer a after it has reached $ff, an overflow is generated, and timer a is reset to $00. the overflow sets the timer a interrupt request flag (ifta: $001, bit 2). timer a continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. registers for timer a operation : timer a operating modes are set by the following registers. timer mode register a (tma: $008): four-bit write-only register that selects timer a? operating mode and input clock source as shown in figure 34.
hd404654 series 49 bit initial value read/write bit name 2 0 w tma2 0 0 w tma0 1 0 w tma1 timer mode register a (tma: $008) 0 0 1 0 1 0 1 0 1 0 1 pss pss pss pss pss pss pss pss operating mode timer a mode tma1 tma2 tma0 source prescaler 2048t cyc 1024t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc input clock frequency 0 1 1 3 not used note: timer counter overflow output period (seconds) = input clock period (seconds) 256. figure 34 timer mode register a (tma) timer c timer c functions: timer c has the following functions. free-running/reload timer watchdog timer timer output operation (toggle, 0, 1, and pwm outputs) the block diagram of timer c is shown in figure 35.
hd404654 series 50 watchdog on flag (wdon) system reset signal timer c interrupt flag (iftc) timer output control logic timer read register cu (trcu) timer output control timer read register cl (trcl) clock timer counter c (tcc) selector system clock prescaler s (pss) overflow internal data bus timer write register cu (twcu) timer write register cl (twcl) timer mode register c1 (tmc1) timer mode register c2 (tmc2) free-running /reload control watchdog timer control logic toc per 2 4 8 32 128 512 1024 2048 3 3 figure 35 block diagram of timer c timer c operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register c1 (tmc1: $00d). timer c is initialized to the value set in timer write register c (twcl: $00e, twcu: $00f) by software and incremented by one at each clock input. if an input clock is applied to timer c after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer c is initialized to its initial value set in timer write register c; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again.
hd404654 series 51 the overflow sets the timer c interrupt request flag (iftc: $002, bit 2). iftc is reset by software or mcu reset. refer to figure 3 and table 1 for details. watchdog timer operation: timer c is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (wdon: $020, bit 1) to 1. if a program routine runs out of control and an overflow is generated, the mcu is reset. program run can be controlled by initializing timer c by software before it reaches $ff. timer output operation: the following four output modes can be selected for timer c by setting timer mode register c2 (tmc2: $014). ? toggle ? 0 output ? 1 output ? pwm output by selecting the timer output mode, pin r3 1 /toc is set to toc. the output from toc is reset low by mcu reset. ? toggle output: when toggle output mode is selected, the output level is inverted if a clock is input after timer c has reached $ff. by using this function and the reload timer function, clock signals can be output at a required frequency for the buzzer. the output waveform is shown in figure 36. ? pwm output: when pwm output mode is selected, timer c provides the variable-duty pulse output function. the output waveform differs depending on the contents of timer mode register c1 (tmc1: $00d) and timer write register c (twcl: $00e, twcu: $00f). the output waveform is shown in figure 36. ? 0 output: when 0 output mode is selected, the output level is pulled low if a clock is input after timer c has reached $ff. note that this function must be used only when the output level is high. ? 1 output: when 1 output mode is selected, the output level is set high if a clock is input after timer c has reached $ff. note that this function must be used only when the output level is low.
hd404654 series 52 t (n + 1) t 256 t t (256 ?n) tmc13 = 0 the waveform is always fixed low when n = $ff. t: n: tmc13 = 1 input clock period to counter (figures 37 and 44) the value of the timer write register notes: tmd13 = 0 tmd13 = 1 256 clock cycles 256 clock cycles free-running timer toggle output waveform (timers c, and d) pwm output waveform (timers c and d) (256 ?n) clock cycles (256 ?n) clock cycles reload timer figure 36 timer output waveform registers for timer c operation: by using the following registers, timer c operation modes are selected and the timer c count is read and written. ? timer mode register c1 (tmc1: $00d) ? timer mode register c2 (tmc2: $014) ? timer write register c (twcl: $00e, twcu: $00f) ? timer read register c (trcl: $00e, trcu: $00f) timer mode register c1 (tmc1: $00d): four-bit write-only register that selects the free- running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 37. it is reset to $0 by mcu reset.
hd404654 series 53 writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register c1 write instruction. setting timer c? initialization by writing to timer write register c (twcl: $00e, twcu: $00f) must be done after a mode change becomes valid. bit initial value read/write bit name 3 0 w tmc13 2 0 w tmc12 0 0 w tmc10 1 0 w tmc11 timer mode register c1 (tmc1: $00d) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 1024t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmc12 tmc10 tmc11 tmc13 0 1 free-running/reload timer selection free-running timer reload timer input clock period figure 37 timer mode register c1 (tmc1) timer mode register c2 (tmc2: $014): three-bit read/write register that selects the timer c output mode as shown in figure 38. it is reset to $0 by mcu reset.
hd404654 series 54 bit initial value read/write bit name 3 not used 2 0 r/w tmc22 0 0 r/w tmc20 1 0 r/w tmc21 timer mode register c2 (tmc2: $014) tmc22 0 tmc21 r3 1 /toc mode selection r3 1 toc toc toc toc r3 1 port toggle output 0 output 1 output inhibited pwm output tmc20 0 1 0 1 0 1 0 1 0 1 10 1 figure 38 timer mode register c2 (tmc2) timer write register c (twcl: $00e, twcu: $00f): write-only register consisting of a lower digit (twcl) and an upper digit (twcu) as shown in figures 39 and 40. the lower digit is reset to $0 by mcu reset, but the upper digit value is invalid. timer c is initialized by writing to timer write register c (twcl: $00e, twcu: $00f). in this case, the lower digit (twcl) must be written to first, but writing only to the lower digit does not change the timer c value. timer c is initialized to the value in timer write register c at the same time the upper digit (twcu) is written to. when timer write register c is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer c. bit initial value read/write bit name 3 0 w twcl3 2 0 w twcl2 0 0 w twcl0 1 0 w twcl1 timer write register c (lower digit) (twcl: $00e) figure 39 timer write register c lower digit (twcl)
hd404654 series 55 bit initial value read/write bit name 3 undefined w twcu3 2 undefined w twcu2 0 undefined w twcu0 1 undefined w twcu1 timer write register c (upper digit) (twcu: $00f) figure 40 timer write register c upper digit (twcu) timer read register c (trcl: $00e, trcu: $00f): read-only register consisting of a lower digit (trcl) and an upper digit (trcu) that holds the count of the timer c upper digit as shown in figures 41 and 42. the upper digit (trcu) must be read first. at this time, the count of the timer c upper digit is obtained, and the count of the timer c lower digit is latched to the lower digit (trcl). after this, by reading trcl, the count of timer c when trcu is read can be obtained. bit initial value read/write bit name 3 undefined r trcl3 2 undefined r trcl2 0 undefined r trcl0 1 undefined r trcl1 timer read register c (lower digit) (trcl: $00e) figure 41 timer read register c lower digit (trcl) bit initial value read/write bit name 3 undefined r trcu3 2 undefined r trcu2 0 undefined r trcu0 1 undefined r trcu1 timer read register c (upper digit) (trcu: $00f) figure 42 timer read register c upper digit (trcu) timer d timer d functions: timer d has the following functions. free-running/reload timer external event counter timer output operation (toggle, 0, 1, and pwm outputs) input capture timer the block diagram for each operation mode of timer d is shown in figures 43 (a) and (b).
hd404654 series 56 timer d interrupt request flag (iftd) timer output control logic timer read register du (trdu) timer output control timer read register dl (trdl) clock timer counter d (tcd) selector system clock prescaler s (pss) overflow internal data bus timer write register du (twdu) timer write register dl (twdl) timer mode register d1 (tmd1) timer mode register d2 (tmd2) free-running/ reload control tod edge detection logic edge detection selection register 2 (esr2) edge detection control per 2 3 3 2 4 8 32 128 512 2048 evnd figure 43 (a) block diagram of timer d (free-running/reload timer)
hd404654 series 57 selector 2 4 8 32 128 512 2048 3 2 per input capture status flag (icsf) input capture error flag (icef) timer d interrupt request flag (iftd) error control logic edge detection logic timer read register du (trdu) timer read register dl (trdl) read signal clock timer counter d (tcd) overflow system clock edge detection control prescaler s (pss) input capture timer control timer mode register d1 (tmd1) timer mode register d2 (tmd2) edge detection selection register 2 (esr2) evnd internal data bus figure 43 (b) block diagram of timer d (in input capture timer mode) timer d operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register d1 (tmd1: $010).
hd404654 series 58 timer d is initialized to the value set in timer write register d (twdl: $011, twdu: $012) by software and incremented by one at each clock input. if an input clock is applied to timer d after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer d is initialized to its initial value set in timer write register d; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer d interrupt request flag (iftd: $003, bit 0). iftd is reset by software or mcu reset. refer to figure 3 and table 1 for details. external event counter operation: timer d is used as an external event counter by selecting the external event input as an input clock source. in this case, pin r4 0 /evnd must be set to evnd by port mode register c (pmrc: $025). either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (esr2: $027). when both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. timer d is incremented by one at each detection edge selected by detection edge select register 2 (esr2: $027). the other operation is basically the same as the free-running/reload timer operation. timer output operation: the following four output modes can be selected for timer d by setting timer mode register d2 (tmd2: $015). ? toggle ? 0 output ? 1 output ? pwm output by selecting the timer output mode, pin r3 2 /tod is set to tod. the output from tod is reset low by mcu reset. ? toggle output: the operation is basically the same as that of timer-c? toggle output. ? 0 output: the operation is basically the same as that of timer-c? 0 output. ? 1 output: the operation is basically the same as that of timer-c? 1 output. ? pwm output: the operation is basically the same as that of timer-c? pwm output. input capture timer operation: the input capture timer counts the clock cycles between trigger edges input to pin evnd. either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (esr2: $027). when a trigger edge is input to evnd, the count of timer d is written to timer read register d (trdl: $011, trdu: $012), and the timer d interrupt request flag (iftd: $003, bit 0) and the input capture status flag (icsf: $021, bit 0) are set. timer d is reset to $00, and then incremented again. while icsf is set, if a trigger input edge is applied to timer d, or if timer d generates an overflow, the input capture error flag (icef: $021, bit 1) is set. icsf and icef are reset to 0 by mcu reset or by writing 0. by selecting the input capture operation, pin r3 2 /tod is set to r3 2 and timer d is reset to $00.
hd404654 series 59 registers for timer d operation: by using the following registers, timer d operation modes are selected and the timer d count is read and written. ? timer mode register d1 (tmd1: $010) ? timer mode register d2 (tmd2: $015) ? timer write register d (twdl: $011, twdu: $012) ? timer read register d (trdl: $011, trdu: $012) ? port mode register c (pmrc: $025) ? detection edge select register 2 (esr2: $027) timer mode register d1 (tmd1: $010): four-bit write-only register that selects the free- running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 44. it is reset to $0 by mcu reset. writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register d1 (tmd1: $010) write instruction. setting timer d? initialization by writing to timer write register d (twdl: $011, twdu: $012) must be done after a mode change becomes valid. when selecting the input capture timer operation, select the internal clock as the input clock source. bit initial value read/write bit name 3 0 w tmd13 2 0 w tmd12 0 0 w tmd10 1 0 w tmd11 timer mode register d1 (tmd1: $010) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmd12 tmd10 tmd11 input clock period and input clock source r4 0 /evnd (external event input) tmd13 0 1 free-running/reload timer selection free-running timer reload timer figure 44 timer mode register d1 (tmd1) timer mode register d2 (tmd2: $015): four-bit read/write register that selects the timer d output mode and input capture operation as shown in figure 45. it is reset to $0 by mcu reset.
hd404654 series 60 bit initial value read/write bit name 3 0 r/w tmd23 2 0 r/w tmd22 0 0 r/w tmd20 1 0 r/w tmd21 timer mode register d2 (tmd2: $015) tmd22 tmd20 0 1 0 1 0 1 0 1 tmd21 0 1 0 1 0 1 r3 2 /tod mode selection r3 2 tod tod tod tod r3 2 r3 2 port toggle output 0 output 1 output inhibited pwm output input capture (r3 2 port) tmd23 0 1 don? care don? care don? care figure 45 timer mode register d2 (tmd2) timer write register d (twdl: $011, twdu: $012): write-only register consisting of a lower digit (twdl) and an upper digit (twdu) as shown in figures 46 and 47. the operation of timer write register d is basically the same as that of timer write register c (twcl: $00e, twcu: $00f). bit initial value read/write bit name 3 0 w twdl3 2 0 w twdl2 0 0 w twdl0 1 0 w twdl1 timer write register d (lower digit) (twdl: $011) figure 46 timer write register d lower digit (twdl)
hd404654 series 61 bit initial value read/write bit name 3 undefined w twdu3 2 undefined w twdu2 0 undefined w twdu0 1 undefined w twdu1 timer write register d (upper digit) (twdu: $012) figure 47 timer write register d upper digit (twdu) timer read register d (trdl: $011, trdu: $012): read-only register consisting of a lower digit (trdl) and an upper digit (trdu) as shown in figures 48 and 49. the operation of timer read register d is basically the same as that of timer read register c (trcl: $00e, trcu: $00f). when the input capture timer operation is selected and if the count of timer d is read after a trigger is input, either the lower or upper digit can be read first. bit initial value read/write bit name 3 undefined r trdl3 2 undefined r trdl2 0 undefined r trdl0 1 undefined r trdl1 timer read register d (lower digit) (trdl: $011) figure 48 timer read register d lower digit (trdl) bit initial value read/write bit name 3 undefined r trdu3 2 undefined r trdu2 0 undefined r trdu0 timer read register d (upper digit) (trdu: $012) 1 undefined r trdu1 figure 49 timer read register d upper digit (trdu) port mode register c (pmrc: $025): write-only register that selects r4 0 /evnd pin function as shown in figure 50. it is reset to $0 by mcu reset.
hd404654 series 62 bit initial value read/write bit name 3 0 w pmrc3 2 0 w pmrc2 0 not used 1 0 w pmrc1 pmrc1 0 1 r4 0 /evnd mode selection r4 0 evnd port mode register c (pmrc: $025) pmrc3 0 1 d 13 / int 0 mode selection d 13 int 0 pmrc2 0 1 d 12 / stopc mode selection d 12 stopc figure 50 port mode register c (pmrc) detection edge select register 2 (esr2: $027): write-only register that selects the detection edge of signals input to pin evnd as shown in figure 51. it is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w esr23 2 0 w esr22 0 not used 1 not used detection edge register 2 (esr2: $027) esr23 0 1 esr22 0 1 0 1 evnd detection edge no detection falling-edge detection rising-edge detection double-edge detection note: both falling and rising edges are detected. * * figure 51 detection edge select register 2 (esr2)
hd404654 series 63 notes on use when using the timer output as pwm output, note the following point. from the update of the timer write register until the occurrence of the overflow interrupt, the pwm output differs from the period and duty settings, as shown in table 23. the pwm output should therefore not be used until after the overflow interrupt following the update of the timer write register. after the overflow, the pwm output will have the set period and duty cycle. table 23 pwm output following update of timer write register pwm output mode timer write register is updated during high pwm output timer write register is updated during low pwm output free running timer write register updated to value n interrupt request timer write register updated to value n interrupt request t (255 ?n) t (n + 1) t (n' + 1) t (255 ?n) t (n + 1) reload timer write register updated to value n interrupt request timer write register updated to value n interrupt request t t (255 ?n) t t t (255 ?n) t
hd404654 series 64 serial interface 1 the mcu has one channel of serial interface. the serial interface serially transfers or receives 8-bit data, and includes the following features. multiple transmit clock sources ? external clock ? internal prescaler output clock ? system clock output level control in idle states serial interface 1 serial data register 1 (sr1l: $006, sr1u: $007) serial mode register 1a (sm1a: $005) serial mode register 1b (sm1b: $028) port mode register a (pmra: $004) miscellaneous register (mis: $00c) octal counter (oc) selector the block diagram of serial interface 1 is shown in figure 52.
hd404654 series 65 selector prescaler s (pss) 2 8 32 128 512 2048 selector i/o control logic idle control logic octal counter (oc) serial interrupt request flag (ifs1) clock serial data register (sr1l/u) serial mode register 1a (sm1a) serial mode register 1b (sm1b) transfer control so 1 sck 1 si 1 system clock internal data bus 3 per 1/2 1/2 figure 52 block diagram of serial interface 1 serial interface operation selecting and changing the operating mode: table 24 lists the serial interfaces?operating modes. to select an operating mode, use one of these combinations of port mode register a (pmra: $004), and serial mode register 1a (sm1a: $005) settings; to change the operating mode of serial interface 1, always initialize the serial interface internally by writing data to serial mode register 1a. note that serial interface 1 is initialized by writing data to serial mode register 1a. refer to the following section registers for serial interface for details.
hd404654 series 66 table 24 serial interface 1 operating modes sm1a pmra bit 3 bit 1 bit 0 operating mode 1 0 0 continuous clock output mode 1 transmit mode 1 0 receive mode 1 transmit/receive mode pin setting: the r4 1 / sck 1 pin is controlled by writing data to serial mode register 1a (sm1a: $005). pins r4 2 /si 1 and r4 3 /so 1 are controlled by writing data to port mode register a (pmra: $004). refer to the following section registers for serial interface for details. transmit clock source setting: the transmit clock source of serial interface 1 is set by writing data to serial mode register 1a (sm1a: $005) and serial mode register 1b (sm1b: $028). refer to the following section registers for serial interface for details. data setting: transmit data of serial interface 1 is set by writing data to serial data register 1 (sr1l: $006, sr1u: $007). receive data of serial interface 1 is obtained by reading the contents of serial data register 1. the serial data is shifted by the transmit clock and is input from or output to an external system. the output level of the so 1 pin is invalid until the first data is output after mcu reset, or until the output level control in idle states is performed. transfer control: serial interface 1 is activated by the sts instruction. the octal counter is reset to 000 by the sts instruction, and it increments at the rising edge of the transmit clock for serial interface. when the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal counter is reset to 000, the serial 1 interrupt request flag (ifs1: $003, bit 2) is set, and the transfer stops. when the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t cyc to 8192t cyc by setting bits 0 to 2 (sm1a0?m1a2) of serial mode register 1a (sm1a: $005) and bit 0 (sm1b0) of serial mode register 1b (sm1b: $028) as listed in table 25.
hd404654 series 67 table 25 serial transmit clock (prescaler output) sm1b sm1a bit 0 bit 2 bit 1 bit 0 prescaler division ratio transmit clock frequency 0000 ? 2048 4096t cyc 1 ? 512 1024t cyc 10 ? 128 256t cyc 1 ? 32 64t cyc 100 ? 8 16t cyc 1 ? 24t cyc 1000 ? 4096 8192t cyc 1 ? 1024 2048t cyc 10 ? 256 512t cyc 1 ? 64 128t cyc 100 ? 16 32t cyc 1 ? 48 tcyc operating states: serial interface 1 has the following operating states; transitions between them are shown in figure 53. ? sts wait state ? transmit clock wait state ? transfer state ? continuous transmit clock output state (only in internal clock mode)
hd404654 series 68 sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) trans fer state (octal counter = 000) mcu reset 00 sm1a write 04 sts instruction 01 transmit clock 02 8 transmit clocks 03 sts instruction (ifs1 1) 05 ? sm1a write (ifs1 1) 06 ? external clock mode sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) transfer state (octal counter = 000) sm1a write 14 sts instruction 11 transmit clock 12 15 sts instruction (ifs1 1) ? 8 transmit clocks 13 internal clock mode continuous transmit clock output state (pmra 0, 1 = 0, 0) sm1a write 18 transmit clock 17 16 note: refer to the operating states section for the corresponding encircled numbers. mcu reset 10 ? sm1a write (ifs1 1) figure 53 serial interface state transitions sts wait state: serial interface 1 enters sts wait state by mcu reset (00, 10 in figure 53). in sts wait state, serial interface 1 is initialized and the transmit clock is ignored. if the sts instruction is then executed (01, 11), serial interface 1 enters transmit clock wait state. transmit clock wait state: transmit clock wait state is the period between sts execution and the falling edge of the first transmit clock. in transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts serial data register 1 (sr1l: $006, sr1u: $007), and enters the serial interface in transfer state. however, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). the serial interface enters sts wait state by writing data to serial mode register 1a (sm1a: $005) (04, 14) in transmit clock wait state. transfer state: transfer state is the period between the falling edge of the first clock and the rising edge of the eighth clock. in transfer state, the input of eight clocks or the execution of the sts instruction sets the octal counter to 000, and the serial interface enters another state. when the sts instruction is executed (05, 15), transmit clock wait state is entered. when eight clocks are input, transmit clock wait
hd404654 series 69 state is entered (03) in external clock mode, and sts wait state is entered (13) in internal clock mode. in internal clock mode, the transmit clock stops after outputting eight clocks. in transfer state, writing data to serial mode register 1a (sm1a: $005) (06, 16) initializes serial interface 1, and sts wait state is entered. if the state changes from transfer to another state, the serial 1 interrupt request flag (ifs1: $003, bit 2) is set by the octal counter that is reset to 000. continuous clock output state (only in internal clock mode): continuous clock output state is entered only in internal clock mode. in this state, the serial interface does not transmit/ receive data but only outputs the transmit clock from the sck 1 pin. when bits 0 and 1 (pmra0, pmra1) of port mode register a (pmra: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. if serial mode register 1a (sm1a: $005) is written to in continuous clock output mode (18), sts wait state is entered. output level control in idle states: when serial interface 1 is in sts instruction wait state, the output of serial output pin so 1 can be controlled by setting bit 1 (sm1b1) of serial mode register 1b (sm1b: $028) to 0 or 1. the output level control example of serial interface 1 is shown in figure 54. note that the output level cannot be controlled in transfer state.
hd404654 series 70 state mcu reset pmra write sm1a write sm1b write sr1l, sr1u write sts instruction sck 1 pin (input) so 1 pin ifs1 sts wait state transmit clock wait state transfer state transmit clock wait state sts wait state port selection external clock selection output level control in idle states dummy write for state transition output level control in idle states data write for transmission undefined lsb msb flag reset at transfer completion external clock mode state mcu reset pmra write sm1a write sm1b write sr1l, sr1u write sts instruction sck 1 pin (output) so 1 pin ifs1 sts wait state transfer state transmit clock wait state sts wait state port selection internal clock selection output level control in idle states data write for transmission output level control in idle states undefined lsb msb flag reset at transfer completion internal clock mode figure 54 example of serial interface 1 operation sequence
hd404654 series 71 transmit clock error detection (in external clock mode): serial interface 1 will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. a transmit clock error of this type can be detected as shown in figure 55. if more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial 1 interrupt request flag (ifs1: $003, bit 2) is set, and transmit clock wait state is entered. at the falling edge of the next normal clock signal, the transfer state is entered. after the transfer is completed and ifs is reset, writing to serial mode register 1a (sm1a: $005) changes the state from transfer to sts wait. at this time serial interface 1 is in the transfer state, and the serial 1 interrupt request flag (ifs1: $003, bit 2) is set again, and therefore the error can be detected. notes on use: initialization after writing to registers: if port mode register a (pmra: $004) is written to in transmit clock wait state or in transfer state, serial interface 1 must be initialized by writing to serial mode register 1a (sm1a: $005) again. serial 1 interrupt request flag (ifs1: $003, bit 2) set: for serial interface 1, if the state is changed from transfer state to another by writing to serial mode register 1a (sm1a: $005) or executing the sts instruction during the first low pulse of the transmit clock, the serial 1 interrupt request flag (ifs1: $003, bit 2) is not set. to set the serial 1 interrupt request flag (ifs1: $003, bit 2), a serial mode register 1a (sm1a: $005) write or sts instruction execution must be programmed to be executed after confirming that the sck 1 pin is at 1, that is, after executing the input instruction to port r4.
hd404654 series 72 transfer completion (ifs1 1) interrupts inhibited ifs1 0 sm1a write ifs1 = 1 transmit clock error processing normal termination ? ? yes no transmit clock error detection flowchart transmit clock error detection procedures state transmit clock wait state transfer state transfer state transmit clock wait state noise transfer state has been entered by the transmit clock error. when sm1a is written, ifs1 is set. flag set because octal counter reaches 000. flag reset at transfer completion. sm1a write 12 3 45678 sck pin (input) ifs1 1 figure 55 transmit clock error detection
hd404654 series 73 registers for serial interface 1 when serial interface 1 operation is selected, serial data is read and written by the following registers. serial mode register 1a (sm1a: $005) serial mode register 1b (sm1b: $028) serial data register 1 (sr1l: $006, sr1u: $007) port mode register a (pmra: $004) miscellaneous register (mis: $00c) serial mode register 1a (sm1a: $005): this register has the following functions (figure 56). r4 1 / sck 1 pin function selection serial interface 1 transmit clock selection serial interface 1 prescaler division ratio selection serial interface 1 initialization serial mode register 1a is a 4-bit write-only register. it is reset to $0 by mcu reset. a write signal input to serial mode register 1a (sm1a: $005) discontinues the input of the transmit clock to serial data register 1 (sr1l: $006, sr1u: $007) and the octal counter, and the octal counter is reset to 000. therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (ifs1: $003, bit 2) is set. written data is valid from the second instruction execution cycle after the write operation, so the sts instruction must be executed at least two cycles after that.
hd404654 series 74 bit initial value read/write bit name 3 0 w sm1a3 2 0 w sm1a2 0 0 w sm1a0 1 0 w sm1a1 serial mode register 1a (sm1a: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 sm1a2 sm1a0 sm1a1 sm1a3 0 1 r4 1 / sck 1 mode selection r4 1 sck 1 sck 1 output output input clock source prescaler system clock external clock prescaler division ratio refer to table 25 figure 56 serial mode register 1a (sm1a) serial mode register 1b (sm1b: $028): this register has the following functions (figure 57). serial interface 1 prescaler division ratio selection serial interface 1 output level control in idle states serial mode register 1b is a 2-bit write-only register. it cannot be written during data transfer. by setting bit 0 (sm1b0) of this register, the serial interface 1 prescaler division ratio is selected. only bit 0 (sm1b0) can be reset to 0 by mcu reset. by setting bit 1 (sm1b1), the output level of the so 1 pin is controlled in idle states of serial interface 1. the output level changes at the same time that sm1b1 is written to.
hd404654 series 75 bit initial value read/write bit name 3 not used 2 not used 0 0 w sm1b0 1 undefined w sm1b1 sm1b0 0 1 serial clock division ratio prescaler output divided by 2 prescaler output divided by 4 serial mode register 1b (sm1b: $028) sm1b1 0 1 output level control in idle states low level high level figure 57 serial mode register 1b (sm1b) serial data register 1 (sr1l: $006, sr1u: $007): this register has the following functions (figures 58 and 59) serial interface 1 transmission data write and shift serial interface 1 receive data shift and read writing data in this register is output from the so 1 pin, lsb first, synchronously with the falling edge of the transmit clock; data is input, lsb first, through the si 1 pin at the rising edge of the transmit clock. input/output timing is shown in figure 60. data cannot be read or written during serial data transfer. if a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. bit initial value read/write bit name 3 undefined r/w sr13 2 undefined r/w sr12 0 undefined r/w sr10 1 undefined r/w sr11 serial data register 1 (lower digit) (sr1l: $006) figure 58 serial data register 1 (sr1l) bit initial value read/write bit name 3 undefined r/w sr17 2 undefined r/w sr16 0 undefined r/w sr14 1 undefined r/w sr15 serial data register 1 (upper digit) (sr1u: $007) figure 59 serial data register 1 (sr1u)
hd404654 series 76 lsb msb 12 345 678 transmit clock serial output data serial input data latch timing figure 60 serial interface output timing port mode register a (pmra: $004): this register has the following functions (figure 61). r4 2 /si 1 pin function selection r4 3 /so 1 pin function selection port mode register a is a 4-bit write-only register, and is reset to $0 by mcu reset. bit initial value read/write bit name 0 0 w pmra0 1 0 w pmra1 port mode register a (pmra: $004) pmra0 0 1 r4 3 /so 1 mode selection r4 3 so 1 pmra1 0 1 r4 2 /si 1 mode selection r4 2 si 1 3 not used 2 not used figure 61 port mode register a (pmra)
hd404654 series 77 miscellaneous register (mis: $00c): this register has the following functions (figure 62). r4 3 /so 1 pin pmos control miscellaneous register is a 4-bit write-only register and is reset to $0 by mcu reset. mis2 0 1 r4 3 /so 1 pmos on/off selection on off bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 miscellaneous register (mis: $00c) mis3 0 1 pull-up mos on/off selection off on 1 not used 0 not used figure 62 miscellaneous register (mis)
hd404654 series 78 dtmf generator circuit the mcu provides a dual-tone multifrequency (dtmf) generator circuit. the dtmf signal consists of two sine waves to access the switching system. figure 63 shows the dtmf keypad and frequencies. each key enables tones to be generated corresponding to each frequency. figure 64 shows a block diagram of the dtmf circuit. the osc clock (400 khz, 800 khz, 2 mhz, 3.58 mhz or 4 mhz) is changed into four clock signals through the division circuit (1/2, 1/5, 1/9 and 1/10). the dtmf circuit uses one of the four clock signals, which is selected by system clock select register 1 (ssr1: $029) and system clock select register 2 (ssr2: $02a) depending on the osc clock frequency. the dtmf circuit has transformed programmable dividers, sine wave counters, and control registers. the dtmf generation circuit is controlled by the following three registers. 123a 456b 789c * 0# d r1 (697 hz) r2 (770 hz) r3 (852 hz) r4 (941 hz) c1 (1,209 hz) c2 (1,336 hz) c3 (1,477 hz) c4 (1,633 hz) figure 63 dtmf keypad and frequencies
hd404654 series 79 sine wave counter d/a transforma- tion program divider feedback sine wave counter d/a transforma- tion program divider feedback toner vt ref tonec toner output control tonec output control 1/2 1/5 1/9 1/10 f osc tone generator control register (tgc) system clock selection register 1 (ssr1) system clock selection register 2 (ssr2) 400 khz 2 2 2 1 selector tone generator mode register (tgm) internal data bus 400 khz 800 khz 2 mhz 3.58 mhz 4 mhz figure 64 block diagram of dtmf generator circuit
hd404654 series 80 tone generator mode register (tgm: $019): four-bit write-only register, which controls output frequencies as shown in figure 65, and is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w tgm3 2 0 w tgm2 0 0 w tgm0 1 0 w tgm1 tone generator mode register (tgm: $019) tgm3 0 0 1 1 tgm2 0 1 0 1 tonec output frequencies f (1,209 hz) f (1,336 hz) f (1,477 hz) f (1,633 hz) c1 c2 c3 c4 tgm1 0 0 1 1 tgm0 0 1 0 1 toner output frequencies f (697 hz) f (770 hz) f (852 hz) f (941 hz) r1 r2 r3 r4 figure 65 tone generator mode register (tgm) tone generator control register (tgc: $01a): three-bit write-only register, which controls the start/stop of the dtmf signal output as shown in figure 66, and is reset to $0 by mcu reset. toner and tonec output can be independently controlled by bits 2 and 3 (tgc2, tgc3), and the dtmf circuit is controlled by bit 1 (tgc1) of this register. bit initial value read/write bit name 3 0 w tgc3 2 0 w tgc2 0 not used 1 0 w tgc1 tone generator control register (tgc: $01a) tgc1 0 1 dtmf enable bit dtmf disable dtmf enable tgc3 0 1 tonec output control (column) no output tonec output (active) tgc2 0 1 toner output control (row) no output toner output (active) figure 66 tone generator control register (tgc)
hd404654 series 81 system clock select registers 1 and 2 (ssr1: $029, ssr2: $02a): four-bit write-only registers. these registers must be set to the value specified in figures 67 and 68 depending on the frequency of the oscillator connected to the osc 1 and osc 2 pins. note that if the combination of the oscillation frequency and the values in these registers is different from that specified in figures 67 and 68, the dtmf output frequencies will differ from the correct frequencies as listed in table 26. bit initial value read/write bit name 3 not used 2 not used 0 0 w ssr10 1 0 w ssr11 system clock select register 1 (ssr1: $029) ssr22 0 0 0 0 1 400 khz 800 khz 2 mhz 4 mhz 3.58 mhz ssr11 0 0 1 1 ssr10 0 1 0 1 system clock selection : don? care figure 67 system clock select register 1 (ssr1) bit initial value read/write bit name 3 not used 2 0 w ssr22 0 not used 1 not used ssr22 0 serial clock select register 2 (ssr2: $02a) system clock selection selected from 400 khz, 800 khz, 2 mhz, 4 mhz 1 3.58 mhz note: * * refer to system clock select register 1 (ssr1). figure 68 system clock select register 2 (ssr2)
hd404654 series 82 dtmf output: the sine waves of the row-group and column-group are individually converted in the d/a conversion circuit which provides a high-precision ladder resistance. the dtmf output pins (toner, tonec) transmit the sine waves of the row-group and column-group, respectively. figure 69 shows the tone output equivalent circuit. figure 70 shows the output waveform. one cycle of this wave consists of 32 slots. therefore, the output waveform is stable with little distortion. table 26 lists the frequency deviation of the mcu from standard dtmf signals. table 26 frequency deviation of the mcu from standard dtmf fosc = 400 khz, 800 khz, 2 mhz, 4 mhz fosc = 3.58 mhz standard dtmf (hz) mcu (hz) deviation from standard (%) mcu (hz) deviation from standard (%) r1 697 694.44 ?.37 690.58 ?.92 r2 770 769.23 ?.10 764.96 ?.65 r3 852 851.06 ?.11 846.33 ?.67 r4 941 938.97 ?.22 933.75 ?.77 c1 1,209 1,212.12 0.26 1,205.39 ?.30 c2 1,336 1,333.33 ?.20 1,325.92 ?.75 c3 1,477 1,481.48 0.30 1,473.25 ?.25 c4 1,633 1,639.34 0.39 1,630.23 ?.17 notes: this frequency deviation value does not include the frequency deviation due to the oscillator element. also note that in this case the ratio of the high level and low level widths in the oscillator waveform due to the oscillator element will be 50%:50%. switch control vt gnd ref toner tonec figure 69 tone output equivalent circuit
hd404654 series 83 vt ref gnd time slot 1234567891011121314151617181920212223242526272829303132 figure 70 waveform of tone output
hd404654 series 84 comparator the block diagram of the comparator is shown in figure 71. the comparator compares input voltage with the reference voltage. setting 1 to bit 3 (cer3) of the compare enable register (cer: $018) executes a voltage comparison. if an input voltage at comp 0 or comp 1 is higher than the reference voltage, the tm or tmd command sets the status flag (st) high for the corresponding bits of the compare data register (cdr: $017) to comp 0 or comp 1 . on the other hand, if an input voltage at comp 0 or comp 1 is lower than the reference voltage, the tm or tmd command clears the st to 0. selector + com- parator comparator data register (cdr) comparator enable register (cer) internal data bus comp 0 vc 2 ref comp comp 1 figure 71 block diagram of comparator compare enable register (cer: $018): three-bit write-only register which enables comparator operation, and selects the reference voltage and the analog input pin. compare data register (cdr: $017): two-bit read-only register which latches the result of the comparison between the analog input pins and the reference voltage. bits 0 and 1 reflect the results of comparison with comp 0 and comp 1 , respectively. this register can be read only by the tm or tmd command. only bit cer3 corresponds to the analog input pin, which is selected by bits cer0 and cer1. after a compare operation, the data in this register is not retained. note on use: during compare operation, pins rd 0 /comp 0 and rd 1 /comp 1 operate as analog inputs and cannot operate as r ports. the comparator can operate in active mode but is disabled in other modes. re 0 /vc ref cannot operate as an r port when the external input voltage is selected as the reference.
hd404654 series 85 bit initial value read/write bit name 3 0 w cer3 2 not used 0 0 w cer0 1 0 w cer1 compare enable register (cer: $018) cer3 0 digital/analog selection digital input mode: rd /comp 0 , rd /comp 1 operate as r port 01 1 analog input mode: rd /comp 0 , rd /comp 1 operate as analog input cer1 0 0 1 1 analog input pin selection comp 0 comp 1 not used not used cer0 0 1 0 1 01 figure 72 compare enable register bit initial value read/write bit name 3 not used 2 not used 0 r cdr0 1 r cdr1 compare data register (cdr: $017) undefined undefined result of comp 0 comparison result of comp 1 comparison figure 73 compare data register
hd404654 series 86 programmable rom (hd4074654) the hd4074654 is a ztat ? microcomputer with built-in prom that can be programmed in prom mode. prom mode pin description pin no. mcu mode prom mode dp-42s fp-44a pin name i/o pin name i/o 139 rd 0 /comp 0 i ce i 240 rd 1 /comp 1 i oe i 3 41 tonec o 4 42 toner o 543 vt ref iv cc 61 re 0 /vc ref im 1 i 72 test i test i 8 3 osc 1 iv cc 9 4 osc 2 o 10 5 reset i reset i 11 6 gnd i gnd 12 7 d 0 i/o o 13 8 d 1 i/o o 14 9 d 2 i/o v cc 15 10 d 3 i/o v cc 16 11 d 4 i/o o 4 i/o 17 12 d 5 i/o o 5 i/o 18 13 d 6 i/o o 6 i/o 19 14 d 7 i/o o 7 i/o 20 15 d 8 i/o a 13 i 21 16 d 9 i/o a 14 i 22 17 d 12 / stopc ia 9 i 23 18 d 13 / int 0 iv pp 24 19 r0 0 / int 1 i/o m 0 i 25 20 r1 0 i/o a 5 i 26 21 r1 1 i/o a 6 i 27 23 r1 2 i/o a 7 i 28 24 r1 3 i/o a 8 i
hd404654 series 87 pin no. mcu mode prom mode dp-42s fp-44a pin name i/o pin name i/o 29 25 r2 0 i/o a 0 i 30 26 r2 1 i/o a 10 i 31 27 r2 2 i/o a 11 i 32 28 r2 3 i/o a 12 i 33 29 r3 0 i/o a 1 i 34 30 r3 1 /toc i/o a 2 i 35 31 r3 2 /tod i/o a 3 i 36 32 r3 3 i/o a 4 i 37 33 r4 0 /evnd i/o o 0 i/o 38 34 r4 1 / sck 1 i/o o 1 i/o 39 35 r4 2 /si 1 i/o o 2 i/o 40 36 r4 3 /so 1 i/o o 3 i/o 41 37 sel i 42 38 v cc iv cc ?2 nc ?4 nc note: i/o: input/output pin, i: input pin, o: output pin
hd404654 series 88 programming the built-in prom the mcu? built-in prom is programmed in prom mode. prom mode is set by pulling test , m 0 , and m 1 low, and reset low as shown in figure 74. in prom mode, the mcu does not operate, but it can be programmed in the same way as any other commercial 27256-type eprom using a standard prom programmer and a 42-to-28-pin socket adapter. recommended prom programmers and socket adapters of the hd4074654 are listed in table 28. since an hmcs400-series instruction is ten bits long, the hmcs400-series mcu has a built-in conversion circuit to enable the use of a general- purpose prom programmer. this circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. this means that if, for example, 4 kwords of built-in prom are to be programmed by a general-purpose prom programmer, an 8 kbyte address space ($0000?7fff) must be specified. warnings 1. always specify addresses $0000 to $1fff when programming with a prom programmer. if address $2000 or higher is accessed, the prom may not be programmed or verified correctly. set all data in unused addresses to $ff. note that the plastic-package version cannot be erased or reprogrammed. 2. make sure that the prom programmer, socket adapter, and lsi are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the lsi. before starting programming, make sure that the lsi is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. prom programmers have two voltages (v pp ): 12.5 v and 21 v. remember that ztat ? devices require a v pp of 12.5 v?he 21-v setting will damage them. 12.5 v is the intel 27256 setting. programming and verification the built-in prom of the mcu can be programmed at high speed without risk of voltage stress or damage to data reliability. programming and verification modes are selected as listed in table 27. for details of prom programming, refer to the preface section, notes on prom programming. table 27 prom mode selection pin mode ce oe v pp o 0 ? 7 programming low high v pp data input verification high low v pp data output programming inhibited high high v pp high impedance
hd404654 series 89 table 28 recommended prom programmers and socket adapters prom programmer socket adapter manufacturer model name package manufacturer model name data i/o corp. 121b dp-42s hitachi hs4654ess01h aval corp. pkw-1000 fp-44a hitachi hs4654esh01h address a 0 to a 14 data o 0 to o 7 oe ce v pp gnd v cc v cc o 0 to o 7 a 0 to a 14 oe ce v pp reset test m 0 m 1 v cc osc 1 d 2 d 3 hd4074654 vt ref figure 74 prom mode connections
hd404654 series 90 addressing modes ram addressing modes the mcu has three ram addressing modes, as shown in figure 75 and described below. register indirect addressing mode: the contents of the w, x, and y registers (10 bits in total) are used as a ram address. direct addressing mode: a direct addressing instruction consists of two words. the first word contains the opcode, and the contents of the second word (10 bits) are used as a ram address. memory register addressing mode: the memory registers (mr), which are located in 16 addresses from $040 to $04f, are accessed with the lamr and xmra instructions. ap 9 ap 0 w 1 y 0 w register x register y register ram address register direct addressing ap 9 ap 0 ram address direct addressing d 9 d 0 2nd word of instruction opcode 1st word of instruction ap 9 ap 0 ram address memory register addressing m 3 opcode instruction 000100 ap 8 ap 7 ap ap 5 ap 4 6 ap 3 ap 2 ap 1 ap ap ap ap ap ap ap ap 87654321 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 w 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 m 2 m 1 m 0 figure 75 ram addressing modes
hd404654 series 91 rom addressing modes and the p instruction the mcu has four rom addressing modes, as shown in figure 76 and described below. direct addressing mode: a program can branch to any address in the rom memory space by executing the jmpl, brl, or call instruction. each of these instructions replaces the 14 program counter bits (pc 13 ?c 0 ) with 14-bit immediate data. current page addressing mode: the mcu has 64 pages of rom with 256 words per page. a program can branch to any address in the current page by executing the br instruction. this instruction replaces the eight low-order bits of the program counter (pc 7 ?c 0 ) with eight-bit immediate data. if the br instruction is on a page boundary (address 256n + 255), executing that instruction transfers the pc contents to the next physical page, as shown in figure 78. this means that the execution of the br instruction on a page boundary will make the program branch to the next page. note that the hmcs400-series cross macroassembler has an automatic paging feature for rom pages. zero-page addressing mode: a program can branch to the zero-page subroutine area located at $0000 $003f by executing the cal instruction. when the cal instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (pc 5 ?c 0 ), and 0s are placed in the eight high- order bits (pc 13 ?c 6 ). table data addressing mode: a program can branch to an address determined by the contents of four- bit immediate data, the accumulator, and the b register by executing the tbr instruction. p instruction: rom data addressed in table data addressing mode can be referenced with the p instruction as shown in figure 77. if bit 8 of the rom data is 1, eight bits of rom data are written to the accumulator and the b register. if bit 9 is 1, eight bits of rom data are written to the r1 and r2 port output registers. if both bits 8 and 9 are 1, rom data is written to the accumulator and the b register, and also to the r1 and r2 port output registers at the same time. the p instruction has no effect on the program counter.
hd404654 series 92 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2nd word of instruction opcode 1st word of instruction [jmpl] [brl] [call] pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc pc 10 11 12 13 program counter direct addressing zero page addressing d 5 d 4 d 3 d 2 d 1 d 0 instruction [cal] opcode pc 98 pc 76 pc 54 pc 3 pc 1 pc 0 pc pc 10 11 12 13 program counter 00 00 0 0 0 0 pc pc pc pc pc pc 2 b 1 b 0 a 3 a 2 a 1 a 0 accumulator program counter table data addressing pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc 10 11 12 13 b 2 b 3 b register p 3 p 0 [tbr] instruction opcode 0 0 p 2 p 1 pc opcode b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 instruction pc 90 pc pc pc 11 12 13 program counter current page addressing [br] pc 10 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc pc 8 pc p 0 p 1 p 2 p 3 figure 76 rom addressing modes
hd404654 series 93 b 1 b 0 a 3 a 2 a 1 a 0 accumulator referenced rom address address designation ra 9 ra 8 ra 7 ra 6 ra 5 ra 4 ra 3 ra 2 ra 1 ra 0 ra ra ra 10 11 12 13 b 2 b 3 b register 0 0 p 3 p 0 [p] instruction opcode p 2 p 1 ra ro 9 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 bbbb aa a a 3210 3210 if ro = 1 8 accumulator, b register rom data pattern output ro 9 rom data r2 3 r2 2 r2 1 r2 0 r1 3 r1 2 r1 1 r1 0 if ro = 1 9 output registers r1, r2 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 figure 77 p instruction
hd404654 series 94 br aaa aaa nop 256 (n ?1) + 255 256n br aaa br bbb 256n + 254 256n + 255 256 (n + 1) bbb nop figure 78 branching when the branch destination is on a page boundary
hd404654 series 95 absolute maximum ratings item symbol value unit notes supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to v cc + 0.3 v total permissible input current ? i o 80 ma 2 total permissible output current ? i o 50 ma 3 maximum input current i o 4 ma 4, 5 30 ma 4, 6 maximum output current ? o 4 ma 7, 8 20 ma 7, 9 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c notes: permanent damage may occur if these absolute maximum ratings are exceeded. normal operation must be under the conditions stated in the electrical characteristics tables. if these conditions are exceeded, the lsi may malfunction or its reliability may be affected. 1. applies to d 13 (v pp ) of the hd4074654. 2. the total permissible input current is the total of input currents simultaneously flowing in from all the i/o pins to gnd. 3. the total permissible output current is the total of output currents simultaneously flowing out from v cc to all i/o pins. 4. the maximum input current is the maximum current flowing from each i/o pin to gnd. 5. applies to d 0 ? 3 , and r0?4. 6. applies to d 4 ? 9 . 7. the maximum output current is the maximum current flowing out from v cc to each i/o pin. 8. applies to d 4 ? 9 and r0?4. 9. applies to d 0 ? 3 .
hd404654 series 96 electrical characteristics dc characteristics (hd404652, hd404654: v cc = 1.8 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c; hd4074654: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes input high voltage v ih reset , stopc , int 0 , int 1 , sck 1, si 1 , evnd 0.9v cc ? cc + 0.3 v osc 1 v cc ?0.3 v cc + 0.3 v external clock input low voltage v il reset , stopc , int 0 int 1 , sck 1 si 1 , evnd ?.3 0.10 v cc v osc 1 ?.3 0.3 v external clock output high voltage v oh sck 1 , so 1 , toc,tod v cc ?1.0 v i oh = 0.5 ma output low voltage v ol sck 1 , so 1 , toc, tod 0.4 v i ol = 0.4 ma i/o leakage current | i il | reset , stopc , int 0 , int 1 , sck 1, si 1 , so 1 , evnd, osc 1 , toc, tod 1 m av in = 0 v to v cc 1 current dissipation in active mode i cc1 v cc ??av cc = 5 v, f osc = 4 mhz digital input mode 2, 5 i cc2 0.6 1.8 ma v cc = 3 v, f osc = 800 khz digital input mode 2, 5 i cmp1 ??av cc = 5 v, f osc = 4 mhz analog comp. mode 3, 5 i cmp2 3.1 4.3 ma v cc = 3 v, f osc = 800 khz analog comp. mode 3, 5 current dissipation in standby mode i sby1 v cc 1.2 ma v cc = 5 v, f osc = 4 mhz 4, 5 i sby2 0.2 0.7 ma v cc = 3 v f osc = 800 khz 4, 5 current dissipation in stop mode i stop v cc ?5 m av cc = 3 v 6
hd404654 series 97 item symbol pin(s) min typ max unit test condition notes stop mode retaining voltage v stop v cc 1.3 v 7 comparator input reference voltage scope vc ref vc ref 0v cc ?1.2 v notes: 1. output buffer current is excluded. 2. i cc1 and i cc2 are the source currents when no i/o current is flowing while the mcu is in reset state. test conditions: mcu: reset pins: reset at gnd (0 to 0.3v) test at v cc (v cc ?.3 to v cc ) 3. rd 0 , rd 1 pins are in analog input mode when no i/o current is flowing. test conditions: mcu: dtmf does not operate pins: rd 0 /comp 0 at gnd (0 v to 0.3 v) rd 1 /comp 1 at gnd (0 v to 0.3 v) re 0 /vc ref at gnd (0 v to 0.3 v) 4. i sby1 and i sby2 are the source currents when no i/o current is flowing while the mcu timer is operating. test conditions: mcu: i/o reset serial interface stopped dtmf does not operate standby mode pins: reset at v cc (v cc ?.3 to v cc ) test at v cc (v cc ?.3 to v cc ) 5. the current dissipation is in proportion to f osc while the mcu is operating or is in standby mode. the current dissipation when f osc = f mhz is given by the following equation: maximum value (f osc = f mhz) = f/4 x maximum value (f osc = 4 mhz) 6. these are the source currents when no i/o current is flowing. test conditions: pins: reset at v cc (v cc ?.3 to v cc ) test at v cc (v cc ?.3 to v cc ) d 13 at v cc (v cc ?.3 to v cc ) * note: * applies to hd4074654. 7. ram data retention.
hd404654 series 98 i/o characteristics for standard pins (hd404652, hd404654: v cc = 1.8 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c; hd4074654: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes input high voltage v ih d 12 ? 13 , r0?d, re 0 0.7v cc ? cc + 0.3 v input low voltage v il d 12 ? 13 , r0?d, re 0 ?.3 0.3v cc v output high voltage v oh r0?4 v cc ?.0 v i oh = 0.5 ma output low voltage v ol r0?4 0.4 v i ol = 0.4 ma i/o leakage current | i il |d 12 , r0?d, re 0 1 m av in = 0 v to v cc 1 d 13 1 m av in = 0 v to v cc 1, 2 1 m av in = v cc ?0.3 v to v cc 1, 3 20 m av in = 0 v to 0.3 v 1, 3 pull-up mos current ? pu r0?4 30 m av cc = 3 v, v in = 0 v input high voltage v iha comp 0 , comp 1 ?c ref +0.05 v analog compare mode 4 input low v ila comp 0 , comp 1 ?c ref ?.05 v analog compare mode 4 notes: 1. output buffer current is excluded. 2. applies to hd404652, hd404654. 3. applies to hd4074654. 4. use an analog input reference voltage in the range 0 v vc ref v cc ?1.2.
hd404654 series 99 i/o characteristics for high-current pins (hd404652, hd404654: v cc = 1.8 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c; hd4074654: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition note input high voltage v ih d 0 ? 9 0.7 v cc ? cc + 0.3 v input low voltage v il d 0 ? 9 ?.3 0.3 v cc v output high voltage v oh d 0 ? 9 v cc ?1.0 v i oh = 0.5 ma d 0 ? 3 2.0 v i oh = 10 ma, v cc = 4.5 v to 6.0 v 2 output low voltage v ol d 0 ? 9 0.4 v i ol = 0.4 ma d 4 ? 9 2.0 v i ol = 15 ma, v cc = 4.5 v to 6.0 v 2 i/o leakage current | i il |d 0 ? 9 1 m av in = 0 v to v cc 1 pull-down mos current i pd d 0 ? 3 ?0 m av cc = 3 v, v in = 3 v pull-up mos current ? pu d 4 ? 9 ?0 m av cc = 3 v, v in = 0 v notes: 1. output buffer current is excluded. 2. when using hd4074654, v cc = 4.5 v to 5.5 v. dtmf characteristics (hd404652, hd404654: v cc = 1.8 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c; hd4074654: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition note tone output voltage (1) v or toner 500 660 mv rms vt ref ?gnd = 2.0 v, r l = 100 k w , v cc = 3.0 v 1 tone output voltage (2) v oc tonec 520 690 mv rms vt ref ?gnd = 2.0 v, r l = 100 k w , v cc = 3.0 v 1 tone output distortion %dis 3 7 % short circuit between toner and tonec r l = 100 k w 2 tone output ratio db cr 2.5 db short circuit between toner and tonec r l = 100 k w 2 notes: 1. see figure 79. 2. see figure 80. these characteristics are guaranteed for an operating frequency (f osc ) of 400 khz, 800 khz, 2 mhz, 3.58 mhz, or 4 mhz.
hd404654 series 100 ac characteristics (hd404652, hd404654: v cc = 1.8 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c; hd4074654: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes clock oscillation frequency f osc osc 1 , osc 2 400 khz 1 800 khz 1 2 mhz 1 3.58 mhz 1 4 mhz 1 instruction cycle time t cyc ? m sf osc = 4 mhz 1/4 division, 2 ? m sf osc = 4 mhz, 1/32 division 3 oscillation stabilization time t rc osc 1 , osc 2 7.5 ms v cc = 2.7 v to 6.0 v 4, 5, 13 (ceramic) 60 ms v cc = 1.8 v to 2.7 v 4, 5, 12 external clock high width t cph osc 1 1100 ns f osc = 400 khz 6 550 ns f osc = 800 khz 6 215 ns f osc = 2 mhz 6 115 ns f osc = 3.58 mhz 6 105 ns f osc = 4 mhz 6 external clock low width t cpl osc 1 1100 ns f osc = 400 khz 6 550 ns f osc = 800 khz 6 215 ns f osc = 2 mhz 6 115 ns f osc = 3.58 mhz 6 105 ns f osc = 4 mhz 6 external clock rise time t cpr osc 1 150 ns f osc = 400 khz 6 75 ns f osc = 800 khz 6 35 ns f osc = 2 mhz 6 25 ns f osc = 3.58 mhz 6 20 ns f osc = 4 mhz 6
hd404654 series 101 item symbol pin(s) min typ max unit test condition notes external clock fall time t cpf osc 1 150 ns f osc = 400 khz 6 75 ns f osc = 800 khz 6 35 ns f osc = 2 mhz 6 25 ns f osc = 3.58 mhz 6 20 ns f osc = 4 mhz 6 int 0 , int 1 , evnd high width t ih int 0 , int 1 , evnd 2t cyc 7 int 0 , int 1 , evnd low width t il int 0 , int 1 , evnd 2t cyc 7 reset low width t rstl reset 2t cyc 8 stopc low width t stpl stopc 1t rc 9 reset rise time t rstr reset 20 ms 8 stopc rise time t stpr stopc 20 ms 9 input capacitance c in all pins except d 13 , d 4 ? 7 15 pf f = 1 mhz, v in = 0 v d 4 ? 7 30 pf d 13 15 pf 180 pf 10 analog comparator stabilization time t cstb comp 0 , comp 1 2 t cyc v cc = 2.7 v to 6.0 v 11, 12 20 t cyc v cc = 1.8 v to 2.7 v notes: 1. bits 0 and 1 (ssr10, ssr11) of system clock select register 1 (ssr1: $029) and bit 2 (ssr22) of system clock select register 2 (ssr2: $02a) must be set according to the system clock frequency. 2. sel = 1 3. sel = 0 4. the oscillation stabilization time is the period required for the oscillator to stabilize after v cc reaches 2.7 v (1.8 v for hd404654 and hd404652) at power-on, after reset input goes low when stop mode is cancelled, or after stopc input goes low when stop mode is cancelled. at power-on or when stop mode is cancelled, reset or stopc must be input for at least t rc to ensure the oscillation stabilization time. if using a ceramic oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance.
hd404654 series 102 5. applies to ceramic oscillator only. when using crystal oscillator: v cc = 2.7 v to 6.0 v, t rc = 40 ms (typ) or v cc = 1.8 v to 2.6 v, t rc = 60 ms (typ) crystal oscillator (osc 1 , osc 2 ) c 1 2 c crystal oscillator gnd l s c r s c 0 f r osc 1 osc 2 osc 2 osc 1 r f = 1 m w 20% c 1 = c 2 = 10?2 pf 20% crystal: equivalent to circuit shown below c 0 = 7 pf max r s = 100 w max f = 400 khz, 800 khz, 2 mhz, 3.58 mhz, 4 mhz since the circuit constants change depending on the crystal or ceramic resonator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. wiring among osc 1 , osc 2 , and elements should be as short as possible, and must not cross other wiring (see figure 20). 6. refer to figure 81. 7. refer to figure 82. 8. refer to figure 83. 9. refer to figure 84. 10. applies to hd4074654. 11. analog comparator stabilization time is the period for the analog comparator to stabilize and for correct data to be read after entering rd 0 /comp 0 and rd 1 /comp 1 into analog input mode. 12. hd4074654 : v cc = 2.7 v to 5.5 v
hd404654 series 103 serial interface timing characteristics (hd404652, hd404654: v cc = 1.8 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c; hd4074654: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) during transmit clock output item symbol pin (s) min typ max unit test condition note transmit clock cycle time t scyc sck 1 1t cyc load shown in figure 86 1 transmit clock high width t sckh sck 1 0.5 t scyc load shown in figure 86 1 transmit clock low width t sckl sck 1 0.5 t scyc load shown in figure 86 1 transmit clock rise time t sckr sck 1 100 ns load shown in figure 86 1 transmit clock fall time t sckf sck 1 100 ns load shown in figure 86 1 serial output data delay time t dso so 1 500 ns load shown in figure 86 1 serial input data setup time t ssi si 1 300 ns 1 serial input data hold time t hsi si 1 300 ns 1 note: 1. refer to figure 85. during transmit clock input item symbol pin (s) min typ max unit test condition note transmit clock cycle time t scyc sck 1 1t cyc 1 transmit clock high width t sckh sck 1 0.5 t scyc 1 transmit clock low width t sckl sck 1 0.5 t scyc 1 transmit clock rise time t sckr sck 1 100 ns 1 transmit clock fall time t sckf sck 1 100 ns 1 serial output data delay time t dso so 1 500 ns load shown in figure 86 1 serial input data setup time t ssi si 1 300 ns 1 serial input data hold time t hsi si 1 300 ns 1 note: 1. refer to figure 85.
hd404654 series 104 r = 100 k w l r = 100 k w l tonec toner gnd figure 79 tone output load circuit r = 100 k w l tonec toner gnd figure 80 distortion db cr load circuit t cpr t cpf v cc ?0.3 v 0.3 v t cph t cpl 1/f cp osc 1 figure 81 external clock timing 0.9 v cc 0.1 v cc int 0 , int 1 , evnd t ih t il figure 82 interrupt timing
hd404654 series 105 t rstr t rstl 0.9 v cc 0.1 v cc reset figure 83 reset timing t stpr t stpl 0.9 v cc 0.1 v cc stopc figure 84 stopc timing 0.9 v cc 0.1 v cc t dso t sckf t sckl t ssi t hsi t scyc t sckr 0.4 v v ?1.0 v cc v ?1.0 v (0.9 v ) * cc 0.4 v (0.1 v ) * sck so si note: * cc v ?1.0 v and 0.4 v are the threshold voltages for transmit clock output. cc cc t sckh 1 1 1 cc 0.9 v and 0.1 v are the threshold voltages for transmit clock output. cc figure 85 serial interface timing
hd404654 series 106 r l = 2.6 k w v cc 1s2074 h or equivalent r 12 k w test point c 30 pf figure 86 timing load circuit
hd404654 series 107 notes on rom out please pay attention to the following items regard ing rom out. on rom out, fill the rom area indicated below with 1s to create the same data size as 4-kword version (hd404654). a 4-kword data size is required to change rom data to mask manufacturing data since the program used is for a 4-kword version. this limitation applies when using an eprom or a data base. fill this area with all 1s vector address zero-page subroutine (64 words) pattern and program (2048 words) not used rom 2-kword version: hd404652 address $0800 to $0fff $0000 $000f $0010 $003f $0040 $07ff $0800 $0fff
hd404654 series 108 hd404652/hd404654 option list please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version). 5. rom code media 7. stop mode used not used 8. package dp-42s fp-44a eprom: the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). eprom: the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. 6. oscillator for osc1 and osc2 ceramic oscillator crystal oscillator external clock f = f = f = mhz mhz mhz date of order customer department name rom code name lsi number 1. rom size please check off the appropriate applications and enter the necessary information. hd404652 hd404654 2-kword 4-kword
hd404654 series 109 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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